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I have created my custom component, it have an avalon slave interface, it have 2 slave registers, how can i access these registers if i have the base address, i mean that what is the order of these internal registers,
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Every register you implement in the custom component is supposed to have an address (or offset) inside the MM slave address range. This depends only on your hw design.
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another question is if this component takes 20 clk cycle to finish, how can i take its output when it just finish.
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Three options:
- wait at least 20 clk with a sw cycle
- implement a status register with a completion flag bit: then poll the bit until the it signals your data is ready; this is especially useful when the process duration is not constant
- route the completion signal to an irq
