avalon_interface

[Altera_Forum]

Hi Everybody, 

 I am a biginnet to NIOS in Altera FPGA's. Our customer has given us some existing code and asked us use the same for present project. This FPGA functionality is some thing to work as a bridge between SPI and I2C interfaces. Processor to FPGA interface is on SPI and FPGA to on-board devices interface is on I2C. So, FPGA has to lookinto SPI command and has to initiate corresponding I2C signal generation from NIOS Core. To support timing requirements of SPI interface.. one DPRAM is used to replicate some of on-board device information.. In read condition, data can read from DPRAM instead of following interface conversion. For some other devices, data has to be read through NIOS and sent to FPGA Logic. Finally, This particular FPGA code which is taking care of Avalon interface, needs to 2 read data interfaces.. One from NIOS core and other from DPRAM. But when i tried to create a component with this FPGA code and declare these 2 signals as writedata avalon interfaces in SOPC Builder, It is giving a error saying "There can be only one signal of type writedata".. Please help me on how to declare these two signals.. Since these 2 signals are inputs to FPGA code i am expecting these two signals as writedata only.  Thanks & Regards, Siva

[Altera_Forum]

This is confusing me a bit... but maybe you want two Avalon bus ports?

[Altera_Forum]

Thanks for your suggestion Mike. 

 If i look into given '.ptf' file.. I could find only one tri_state_bridge in SOPC system. And in PORT_MAP information of vhdl component, 32bit data_from_avalon is declared as writedata and 8bit data_from_dpram as export type. Since data_from_dpram is not fpga i/o's, its has to be from DPRAM component of SOPC system.. How to interface these signals.  Thanks & Regards, Siva

[Altera_Forum]

Okay, you've completely lost me. It looks like you're talking about external RAM, internal dual-port RAM, one or more chunks of on-chip logic, maybe a Nios II processor, an SPI bus, and an I2C bus... and I haven't figured out how you want them hooked up.

[Altera_Forum]

--- Quote Start ---  originally posted by mike desimone@Oct 15 2006, 01:49 PM okay, you&#39;ve completely lost me.  it looks like you&#39;re talking about external ram, internal dual-port ram, one or more chunks of on-chip logic, maybe a nios ii processor, an spi bus, and an i2c bus... and i haven&#39;t figured out how you want them hooked up. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18704)  --- quote end ---    --- Quote End ---     http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif  Same feeling for me http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

[Altera_Forum]

Sorry for creating confusion with out giving complete info... FPGA Flow can be seen in the block diagram as  

   TLS Shelf Controller  | i2c | spi  | |   NIOS PIO SPI_INTERFACE ---- DPRAM  ___|________|______________|____________|___________  Tri-State_Bridge (Avalon Switch)  ________________________________________________  |  |  Flash Slave Interface   TLS: Tunable Laser Source  DPRAM: Internal Dual-Port Ram  SPI_INTERFACE Block is the bridge between processor (on spi interface) and NIOS Core. SPI_INTERFACE looks into present spi-cmd and generates 32bit encoded data and interrupt to NIOS. ISR in NIOS decodes 32bit Code and performs corresponding operation (By generating i2c signals). Central processor operation can be to update 8-bit normal fpga registers or 32bit TLS registers. Since SPI interface is expecting only one clock cycle delay between read cmd and read data.. replica&#39;s of normal register and tls registers are managed in dpram and one 32bit array in NIOS.  So SPI_INTERFACE module requires 32bit data from NIOS and 8bit data from DPRAM. Since SPI_INTERFACE is a component of SOPC system, all i/o ports interface has to declared defined. Since 32bit data is expected from avalon-bus, that port signal type has to be writedata..   I am not very clear on data from DPRAM.. Since DPRAM is also another component of SOPC system.. Should i expect DPRAM data from avalon-bus only?, in that case signal-type has to be &#39;writedata&#39; and 2nd writedata port is not supported by SOPC builder. Or its signal type can be export only..? In that case how to make connection between read-data from dpram module and dpram-rddata of spi_interface. Do we have instantiate DPRAM block again in top-level fpga module? Since it is a part of SOPC system.. It is already present in nios system we are adding in top-level file. I can put my question as   "How to manage data interface between 2 SOPC components??????"   Hope i am a bit clear on FPGA Flow. Actually i am a bit feared that you may not read this post just by looking at the size. Thanks for your patiency to through this.  Block-diagram view is nice in reply window.. Thanks & Regards, Siva

[Altera_Forum]

I tried to give in-detail description on FPGA flow and on my confusion.

[Altera_Forum]

So you need a dedicated data connection between your SPI interface and the dual port RAM. There are 2 solutions for this, either use Avalon switch fabric, or just use external connections between the two. 

 For the first case, you need to have an Avalon master in the SPI interface, in addition to existing slave. The DPRAM module should also have 2 Avalon slave interfaces, instead of one. I&#39;m not using Altera component builder to write my class.ptf files, but if I recall correctly you can create multiple Avalon interfaces (there is a dedicated window tab for this) and assign corresponding signals to them. At the end, add the new modules to SOPC module and connect the SPI master to the dedicated DPRAM slave (no need to connect the Nios master to it, Nios data master needs only connection with the other DPRAM port).  If you prefer to bypass SOPC and Avalon bus in this case, just export all the signals related to this data connection in both SPI and DPRAM&#39;s second port and connect them with wires in Quartus block diagram.  Hope I understood you correctly and good luck with this!

[Altera_Forum]

Thanks a lot Clancy.. These two options are interesting and 2nd option is looking simple.. For this project i will proceed with option 2.. and explore 1st option later. 

 Thanks & Regards, Siva