dataavailable signal on Avalon MM

[Altera_Forum]

I have a MM slave that has to read an external device, and due to the latency in the read process to this device, I would like to have my Nios initiate the process by a write to a register and then release the bus. When the data is ready is it as simple as asserting the dataavailable signal on the slave interface and then Nios will come back and do a read transfer of the data?

[Altera_Forum]

Hi,  

 "dataavailable" is part of the optional (and deprecated) flow control feature. It doen's quite do what you want and it was never supported by NIOS anyway -- NIOS will simply "ignore" the signal.  What you need to do is either a) start the process by writing to a register and then poll (read) a status register to see if it has been completed  b) start the process by writing to a register and then generate an interrupt when it has been completed

[Altera_Forum]

I also have had problems with dataavailable. I've used waitrequest instead. It stalls the bus, but my slave was the only component on the bus, so that was no problem. 

Maybe readdatavalid could be of use. Every read-request must be followed up by a readdatavalid. You can have multiple outstanding read-requests at a time. Check the Avalon MM manual for details. The use of waitrequest is simpler, for sure.  Good luck, Ton

[Altera_Forum]

Remember that the Avalon bus is 'slave arbitrated'. 

So that during the long cycle only the master (nios) and other accesses to the same slave are stalled.

[Altera_Forum]

Like std_logic_vector said this is what the 'readdatavalid' signal is for. It allows the master to post multiple read requests in order to hide the latency. Alternatively if you have bulk data to move from this high latency interface you could use a DMA instead.