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Hi everybody,
I'm working on an implementation of openpowerlink (http://openpowerlink.sourceforge.net/web/openpowerlink/documentation.html) for the de10-nano platform. The powerlink fpga code needs to talk directly to the ethernet phy. The connection works via loanio. Now the ethernet phy needs a 25MHz clock. When I implement a pll feeding the fpga code and the loanio, the fitter complains it can't generate such connection. Is there any way, I could get the same 25MHz clock for the fpga part as for the ethernet phy? Help is very appreciated at this point, many thanks, SimonLink Copied
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I remember seeing some sort of similar issues if I implement SignalTap inside the design. If you have SignalTap, try removing that and see if that helps. If not, try using one of the clocks that are generated from the HPS itself (User Clock 0 or 1)
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--- Quote Start --- I remember seeing some sort of similar issues if I implement SignalTap inside the design. If you have SignalTap, try removing that and see if that helps. If not, try using one of the clocks that are generated from the HPS itself (User Clock 0 or 1) --- Quote End --- I'm not using signal tap. I tried using the HPS clocks aswell, same fitter error. I ended up using a clock divider instead of the pll.

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