de2_system_v1.5 --> tut_DE2_SDRam

[Altera_Forum]

Is there a bug in the sourcecode, which listed in the "tut_DE2_SDRam_vhdl.pdf"-file under  

 ..\DE2_System_v1.5\DE2_tutorials ???  I copy and paste the code in my new project and become the following error message:  Error (10028): Can&#39;t resolve multiple constant drivers for net "BA[0]" at lights.vhd(46)  Are the 2 Lines of vhdl-Code correct?? BA <= (DRAM_BA_1 & DRAM_BA_0); DQM <= (DRAM_UDQM & DRAM_LDQM);  The Tutorial describes: <div class='quotetop'>QUOTE </div>  --- Quote Start ---  Observe that the two Bank Address signals are treated by the SOPC Builder as a two-bit vector called zs_ba_from_the_sdram[1:0], as seen in Figure 6. However, in the DE2_pin_assignments.csv file these signals are given as separate signals DRAM_BA_1 and DRAM_BA_0. Therefore, in our VHDL code, we concatenated these signals as (DRAM_BA_1 & DRAM_BA_0) to form a two-bit vector BA. Similarly, the vector zs_dqm_from_the_sdram[1:0] corresponds to the vectorDQMwhich is formed as (DRAM_UDQM& DRAM_LDQM).[/b]  --- Quote End ---    Please help me...

[Altera_Forum]

Now, I have tested the "Verilog - Version" of the design and that works fine... 

 But i can´t find any mistake in the vhdl program code. Here is the complete source code from the vhdl tutorial, which doesn´t compile right under QuartusII 6.1:  &#8722;&#8722; Inputs: SW7&#8722;0 are parallel port inputs to the Nios II system. &#8722;&#8722; CLOCK_50 is the system clock. &#8722;&#8722; KEY0 is the active-low system reset. &#8722;&#8722; Outputs: LEDG7&#8722;0 are parallel port outputs from the Nios II system. &#8722;&#8722; SDRAM ports correspond to the signals in Figure 2; their names are those &#8722;&#8722; used in the DE2 User Manual. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY lights IS PORT ( SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0); KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0); CLOCK_50 : IN STD_LOGIC; LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) DRAM_CLK, DRAM_CKE : OUT STD_LOGIC; DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); DRAM_BA_1, DRAM_BA_0 : BUFFER STD_LOGIC; DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_WE_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); DRAM_UDQM, DRAM_LDQM : BUFFER STD_LOGIC ); END lights; ARCHITECTURE Structure OF lights IS COMPONENT nios_system PORT ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; out_port_from_the_LEDs : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); in_port_to_the_Switches : IN STD_LOGIC_VECTOR(7 DOWNTO 0) zs_addr_from_the_sdram: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); zs_ba_from_the_sdram: BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0); zs_cas_n_from_the_sdram: OUT STD_LOGIC; zs_cke_from_the_sdram: OUT STD_LOGIC; zs_cs_n_from_the_sdram: OUT STD_LOGIC; zs_dq_to_and_from_the_sdram: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); zs_dqm_from_the_sdram: BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0); zs_ras_n_from_the_sdram: OUT STD_LOGIC; zs_we_n_from_the_sdram: OUT STD_LOGIC ); END COMPONENT; SIGNAL BA : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL DQM : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN BA <= (DRAM_BA_1 & DRAM_BA_0); DQM <= (DRAM_UDQM & DRAM_LDQM); &#8722;&#8722; Instantiate the Nios II system entity generated by the SOPC Builder. NiosII: nios_system PORT MAP (CLOCK_50, KEY(0), LEDG, SW, DRAM_ADDR, BA, DRAM_CAS_N, DRAM_CKE, DRAM_CS_N, DRAM_DQ, DQM, DRAM_RAS_N, DRAM_WE_N ); DRAM_CLK <= CLOCK_50; END Structure;  The lines BA <= .... DQM <= ... seems to be incorrect. Has anyone a solution for me?

[Altera_Forum]

Seems the assignment in VHDL is in the wrong direction. Try 

 DRAM_BA_1 <= BA(1); DRAM_BA_0 <= BA(0); DRAM_UDQM <= DQM(1); DRAM_LDQM <= DQM(0);  instead of  BA <= (DRAM_BA_1 & DRAM_BA_0); DQM <= (DRAM_UDQM & DRAM_LDQM);  And it should work.

[Altera_Forum]

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif  

After many days of looking at SDRAM clock skew details, many trial and error runs (changing clock delays), the answer is below (VHDL coding errror)....  My code now runs from SDRAM with ALTPLL of -3ns.  How do we report this typo to Altera/Terasic? It&#39;s in both versions (1.4 and 1.5) of the documentation I&#39;ve seen.  --------------------------------------------------------------------------------     --- Quote Start ---  originally posted by arrive@Jan 25 2007, 12:18 PM seems the assignment in vhdl is in the wrong direction. try  dram_ba_1 <= ba(1); dram_ba_0 <= ba(0); dram_udqm <= dqm(1); dram_ldqm <= dqm(0);  instead of  ba <= (dram_ba_1 & dram_ba_0); dqm <= (dram_udqm & dram_ldqm);  and it should work. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20876)</div>  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  originally posted by katchins@Feb 7 2007, 03:38 AM http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif  after many days of looking at sdram clock skew details, many trial and error runs (changing clock delays), the answer is below (vhdl coding errror)....  my code now runs from sdram with altpll of -3ns.  how do we report this typo to altera/terasic?  it&#39;s in both versions (1.4 and 1.5) of the documentation i&#39;ve seen.  --- Quote End ---    Altera is aware of the error now and will correct the error in the new release http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif  Thanks for pointing it out.