how to bypass the data cache

[Altera_Forum]

hi, everyone 

i am a beginner of nios2, i have a question about how to bypass the data cache.  my board has 2k bytes data cache, and the net driver of u-boot works error. i don't use hal libary, so i use bit31 methord. in the receive and send functions of net driver, how to bypass the data cache when i access to buffer address.   thans

[Altera_Forum]

Hi, 

  You can allocate the buffer by using fuction: alt_uncached_malloc()  which is discribed in 'NiosII Software Development Handbook'.   Also you can use bit31 method. NiosII CPU can address 4G space, but the higher 2G and the lower 2G are overlaying, the only different is that the higher 2G address will bypass the Cache which means that is the bit31 of address equals to 1, then the access will by pass the Cache.   The third to by pass Cache is IO operations, as the following show: IORD_ALTERA_AVALON_PIO_DATA(base)  IOWR_ALTERA_AVALON_PIO_DATA(base, data)  The HAL provides the C-language macros IORD and IOWR that expand to the appropriate assembly instructions to bypass the data cache. The IORD macro expands to the ldwio instruction, and the IOWR macro expands to the stwio instruction. These macros should be used by HAL device drivers to access device registers.  regards, David

[Altera_Forum]

thanks a lot, i will try first

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  Hi,  You can allocate the buffer by using fuction: alt_uncached_malloc() which is discribed in &#39;NiosII Software Development Handbook&#39;.  Also you can use bit31 method. NiosII CPU can address 4G space, but the higher 2G and the lower 2G are overlaying, the only different is that the higher 2G address will bypass the Cache which means that is the bit31 of address equals to 1, then the access will by pass the Cache.  The third to by pass Cache is IO operations, as the following show: IORD_ALTERA_AVALON_PIO_DATA(base)  IOWR_ALTERA_AVALON_PIO_DATA(base, data)  The HAL provides the C-language macros IORD and IOWR that expand to the appropriate assembly instructions to bypass the data cache. The IORD macro expands to the ldwio instruction, and the IOWR macro expands to the stwio instruction. These macros should be used by HAL device drivers to access device registers.  regards, David[/b]  --- Quote End ---    You should use ath alt_uncached_malloc call or the alt_remap_uncached call. Don&#39;t explicitly set the bit 31 as that&#39;s the current hardware implementation. Besides the functions do just this, the difference is that if the behaviour of the hardware ever changes Altera can change the behaviour of alt_uncached_malloc or alt_remap_uncached and you don&#39;t need to change your code

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  You should use ath alt_uncached_malloc call or the alt_remap_uncached call. Don&#39;t explicitly set the bit 31 as that&#39;s the current hardware implementation. Besides the functions do just this, the difference is that if the behaviour of the hardware ever changes Altera can change the behaviour of alt_uncached_malloc or alt_remap_uncached and you don&#39;t need to change your code[/b]  --- Quote End ---    Hi Rugbybloke,   Great advice...  Thanks a lot...   Have you ever used FS2 console?

[Altera_Forum]

i am modify the net driver of u-boot now, for i need tftp linux kernel after u-boot start. there is 2k dcache in my board, if i use hal libary, where can download this libary?

[Altera_Forum]

which address should set bit-31 to bypass the dcache in open_eth.c of u-boot

[Altera_Forum]

> after u-boot start. there is 2k dcache in my board, if i use hal libary, where 

> can download this libary?  There is no need to use the HAL for u-boot. You can use the CACHE_BYPASS macro (not recommended), readx/writex (asm/io.h), or the flush_dache() operation (asm/cache.h) -- depending on what you are trying to do.  If your device is capable of acting as a bus master, you should use the u-boot flush_dcache operation after initializing a transmit buffer, or before passing a receive buffer to the bus master (make sure the rx buffer is invalidated).  If your device is not capable of acting as a bus master, you have no need to use any of the cache bypass macros when reading/writing the buffer -- only for reading or writing the hardware registers.  Regards, --Scott