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intel Cyclone 10 GX NIOS-II I2C Slave problem

ENG1999
Beginner
1,277 Views

Hello

I made a NIOS-II i2c slave on the Cyclone 10 GX according to the NIOS-II API doc.
The I2C Slave function is work good.
It can receive the data from the I2C master.
Automatically write received information to "slave_mem"(on chip memory).

As a I2C Slave, how do I know when the I2C Master has transport the data for me?
I need to keep refreshing "slave_mem"(on chip memory) data to know which bytes data change?

Does I2C Slave or "slave_mem"(on chip memory) have any callback function that can be used?

 

Thanks ^_^

 

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1 Solution
KellyJialin_Goh
Employee
1,184 Views

Hi,

We do not have an I2C slave IP unfortunately, but with the I2C Host IP in your design, other peripherals connected to the I2C are considered as the slaves already.

Maybe you could try to determine the master and slave by determining what devices will be connected to the I2C bus, which will be the master and what is the use case.


Hope this could clear your doubts. Thank you.


Regards,

Kelly


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7 Replies
KellyJialin_Goh
Employee
1,227 Views

Hi,

Greetings and welcome to Intel' forum.

You may refer to this link to include the library and interface with the IP with the following function calls.

https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/fpga-i2c-host-core-api.html


You may also refer to this link for pin definition:

https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/interface-13852.html


Thank you.

Regards,

Kelly



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ENG1999
Beginner
1,222 Views

Hi Kelly

Thanks for your reply.

 

Can the IP group of fpga-i2c-host-core-api be used as an I2C Slave?

I Saw that the naming method of IP contains "HOST".
I thought HOST meant I2C Master.

 

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KellyJialin_Goh
Employee
1,202 Views

Hi,

The Intel FPGA Avalon® I2C (Host) core (altera_avalon_i2c ) is an IP which implements the I2C protocol. It supports only host mode with a bit-rate up to 400 kbits/s (fast mode) and it can also operate in a multi-host system. It has an Avalon® Memory-Mapped ( Avalon® -MM) agent interface for a host processor to access its control, status, command and data FIFO. Command and data FIFO can be configured to be accessible by either the Avalon® -MM or Avalon® Streaming ( Avalon® -ST). On the serial interface side, it provides two data and clock lines to communicate to remote I2C devices.


Thank you.

Regards,

Kelly


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ENG1999
Beginner
1,193 Views

Hi Kelly

 

If I need to make an I2C Slave device.

Which I2C IP can I use @@?~~

 

Thank you ^_^

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KellyJialin_Goh
Employee
1,185 Views

Hi,

We do not have an I2C slave IP unfortunately, but with the I2C Host IP in your design, other peripherals connected to the I2C are considered as the slaves already.

Maybe you could try to determine the master and slave by determining what devices will be connected to the I2C bus, which will be the master and what is the use case.


Hope this could clear your doubts. Thank you.


Regards,

Kelly


ENG1999
Beginner
1,181 Views

Hi Kelly

Thanks for your reply. I really appreciate it. ^_^

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KellyJialin_Goh
Employee
1,150 Views

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


Thank you.

Regards,

Kelly Jialin, GOH


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