"Taking the SDRAM bridge out of reset"

[Altera_Forum]

Hello everyone, 

 (using DE0-Nano-SoC w/ Cyclone V SoC) First of, I am relatively new to SoC design and to working with Altera products. I am trying to accomplish a project where I am moving data from the FPGA to the DDR3, and was thinking of using the fps-sdram bridge available. But I am a bit confused. In some places I read info on how it is very necessary to take the FPGA-SDRAM bridge out of reset (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/important_note_about_fpgahps_sdram_bridge) But in the posts and examples I find online, using the sdram bridge, there is almost no mention of taking the port out of reset. This leaves me a bit confused. Whats the deal when using the FPGA-SDRAM bridge? Does it require special attention when using it or can it be treated like a normal bridge (set everything up in Qsys and go)  And if it is indeed necessary to initialize the port, is there sample code present, or a standard procedure to follow? Maybe a premade script somewhere (since taking the port out of reset should be a pretty standardised procedure?)  (Because I found a lot of topics on this subject, I will link some projects demonstrating the use of the bridge. Making it easier for people in the future should they stumble across this topic: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory)

[Altera_Forum]

I stumbled across this explanation, https://www.altera.com/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html?utm_source=altera&utm_medium=newsletter&utm_campaign=facts&utm_content=na_how_can_i_enable_ki_15_08_2016 

 adding "run bridge_enable_handoff" to the u-boot should take care of it when using SoCEDS13.1 or newer. EDIT: RUNNING ONLY THE BRIDGE_ENABLE_HANDOFF WILL NOT WORK IN SOME CASES. PLEASE REFER TO: http://www.alteraforum.com/forum/showthread.php?t=51200 THIS WORKED FOR ME!    a small remark on what is mentioned in this topic; I ran : setenv fpga2sdram_handoff 0x311 saveenv run bridge_enable_handoff  After this i programmed the FPGA and booted linux.  after this i was able to use the F2S port to write to SDRAM  I also added these lines to my u-boot.scr