In 5.0 it's a bit tricky since the linker is going to see two memory ports with the same address span. In 6.0 this is easier and you can use configurations like .text in port s1 and all the other sections go in port s2 (system library properties). You would then connect the instruction master to port s1 and the data master to port s2. If nothing else needs to access this memory then you might as well use tightly coupled masters to access this memory (low latency). The nice thing about this setup is .text shouldn't overlap any other section (so no read-write to the same location is possible), and Nios II will be able to access the instruction and data memory in parallel. Just make sure you don't connect a single master (of any kind, not just Nios II) to both ports of a memory.
If you want to try this out I recommend modifying the 'fast' example design hardware (dual port the memory, and connect one of the masters to the other port). Also there is nothing special to implement in software since all instruction (read) accesses use the instruction master and all data accesses (read/write) use the data master. So making good use of dual port memory is up to how you design the system.
