Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12595 Discussions

triple speed ethernet upgrading to nios ii/f problem

Altera_Forum
Honored Contributor II
1,244 Views

Hi, 

 

I am working on a project on a DE2-115 board that involves both a NIOS processor and the triple speed Ethernet IP core , the problem is that nios ii/e processor works well with the mentioned IP core but when trying to upgrade the processor to nios ii/f it doesn't work and it hangs at the step doing the software reset to the PHY chip. 

 

Do anyone have the same issue, or have any suggestion for fixing this issue ? 

 

Thanks in advance and highly appreciate your response.
0 Kudos
9 Replies
Altera_Forum
Honored Contributor II
446 Views

Are the Nios II/f and Ethernet IP core running at the same frequency? If they are not in the same frequency, try adding a clock crossing bridge in between them.

0 Kudos
Altera_Forum
Honored Contributor II
446 Views

Thanks mikedsouze for your reply. 

 

Yes, they are working at the same clock domain (100 MHZ). 

 

Even when I applied the provided example by Altera " Using Triple-Speed Ethernet on DE2-115 Boards " it only works with the NIOS ii/e and doesn't work with NIOS ii/f. 

 

appreciate your help.
0 Kudos
Altera_Forum
Honored Contributor II
446 Views

Can the system runs "Hello world" ?

0 Kudos
Altera_Forum
Honored Contributor II
446 Views

 

Yes I can run the hello world in case if I bypass this step "phy software reset ", cause the program runs infinitely through the while loop of the mentioned step
0 Kudos
Altera_Forum
Honored Contributor II
446 Views

Hi,Actually i've the same problem but with the DE4. The TSE Tutorial provided by Altera use the NiosII/s classic processor, but when it's upgraded to NiosII/f the same software application stall in PCS reset and MAC reset, so i made the configuration steps described on ug_ethernet.pdf (TSE User Guide) and neither worked. I'm trying to figure out where/what's the problem here too.

0 Kudos
Altera_Forum
Honored Contributor II
446 Views

Thanks jnasselle for your update , I have done also several trials (putting a clock bridge between NIOS and TSE , clock crossing bridge ) but unfortunately it doesn't work. 

anyway thanks again, I will keep trying, and pls let me know if you reach to anything regarding this issue and I will do the same as well
0 Kudos
Altera_Forum
Honored Contributor II
446 Views

Hi, 

 

The solution was to disable the data cache of the NiosII/f :)
0 Kudos
Altera_Forum
Honored Contributor II
446 Views

Hi jnasselle 

 

Thanks alot, You really made my day :) 

 

I wanna be your friend ;) 

0 Kudos
Altera_Forum
Honored Contributor II
446 Views

Disabling the Data-cache makes the /f compatible with /s. 

 

For compatibility between Nios II/s you will need t o set the following settings in Nios II/f: 

No Data cache 

No Tightly Coupled Data master 

Static branch prediction 

No MMU/MPU support 

Internal Interrupt Controller 

No shadow register
0 Kudos
Reply