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DSP utilization is limited to 25% when I use aoc to compile OpenCL kernel

 When I use aoc to compile OpenCL kernel ,DSP utilization is limited to 25% .

At first , I used "#pragma unroll" to unroll the loop.  when the number of unroll become bigger ,  The DSP blocks utilization increased.

But,when the number of unroll is bigger enough ,the DSP blocks utilization  is limited to 25% .

Why does this happen?

board:Intel® Programmable Acceleration Card with Intel® Arria® 10 FPGA GX

SDK:Intel FPGA SDK for OpenCL 17.1

aoc compile report:

+--------------------------------------------------------------------+
; Estimated Resource Usage Summary                     ;
+----------------------------------------+---------------------------+
; Resource                                 + Usage                    ;
+----------------------------------------+---------------------------+
; Logic utilization                      ;   78%                     ;
; ALUTs                                     ;   48%                     ;
; Dedicated logic registers       ;   34%                     ;
; Memory blocks                      ;   57%                     ;
; DSP blocks                             ;   25%                     ;
+----------------------------------------+---------------------------;

aoc compile report(when number of unroll become bigger):

+--------------------------------------------------------------------+
; Estimated Resource Usage Summary                     ;
+----------------------------------------+---------------------------+
; Resource                               + Usage                    ;
+----------------------------------------+---------------------------+
; Logic utilization                      ;  176%                    ;
; ALUTs                                     ;  130%                    ;
; Dedicated logic registers       ;   60%                     ;
; Memory blocks                      ;   74%                    ;
; DSP blocks                             ;   25%                     ;
+----------------------------------------+---------------------------;
 

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Hello CaiL,

I recommend taking a look at the Intel® Arria forums... FPGA stakeholders within Intel have more visibility there. You may also want to search the preexisting topics as there are a few different discussions on your topic.

This thread may address some of your questions.

-MichaelC

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