HD 4000 peer to peer DMA errors

[rictripper]

Hello developers,

We are currently investigating a low latency input to output system using your integrated HD 4000 GPU technologies.

Unfortunately we have discovered an issue when transferring data directly to the physical memory on the graphics module form a PCIe capture card.

Background:

The picture ( http://www.datapath.co.uk/Vision/20131126_163932.jpg ) depicts a DMA operation from a capture (input) driver directly to an Intel integrated GPU (output). The scatter gather buffer is generated from a virtual address and length passed to the driver via ksproxy (DirectShow streaming). We also see the error using other interfaces including DirectX9 and assume that the error must be related to the hardware DMA operation. The peep-to-peer DMA works without error on non Intel GPU's such as AMD and NVIDIA.

Driver operation:

A virtual address is locked by the driver and a scatter gather table created for the underlying physical memory.

We use Windows provided routines to lock and create the scatter gather tables:

-MmProbeAndLockPages

-GetScatterGatherList

We have tried a 'memset' command on the virtual buffer prior to a DMA in an attempt to invoke the 'swizzle table' as we are not using a front door method to copy the data. We appreciate that the GPU back buffer will reside in system memory and accessed via the 'swizzle table'.

The data in the attached image looks to be in tiles. If we copy via system memory the error does not exist.

The data in the image is live (movement within the tiles) when a camera is used as an input source.

Can you provide any information to help us resolve the issue?

Thank you very much in advance, Rich.

[ROBERT_U_Intel]

Hi Rich

I will forward this information to our DirectX developers.

Thanks

Robert

[rictripper]

Thanks Robert, I'll watch this space.

[rictripper]

Hello Robert, any information on this thread from the DirectX developers, I guess its a quick answer from the right person?

[rictripper]

Any news on this error Robert:

http://www.datapath.co.uk/tbd/vision/20131126_163932.jpg

Customers are now reporting this as an error?

[ROBERT_U_Intel]

Hi Rich

Still working on finding the correct engineer to address the issue. Please stay tuned.

Robert

[rictripper]

Hello Robert,

After reproducing the error in both DirectShow (VMR7, VMR9 & EVR) we continued our focus back within DirectX.

We created a number of textures in addition to the backbuffers, filled the textures with a peer to peer DMA then StretchRect into the backbuffer.

This also exhibited the error seen in the image attached above.

We have committed much time to this error, assistance is appreciated.

Intel has a significant advantage using this mechanism for low latency applications.

Richard Lince,

[rictripper]

Robert?

Will performing/forcing a colour space conversion in hardware force the display to non-tiled linear data display?

Richard.

[ROBERT_U_Intel]

Hi Richard

Could you please provide the following information:

1. What version of graphics driver are you using?
2. What OS are you using?
3. Do you see the issue on newer version of Intel HD graphics (Haswell based)?
4. Can you attach the DXdiag report for the system you are seeing the issue on?

Thanks

Robert

[Michael_M_5]

Hi Robert,

On the test machine I am using I have the following:

    * Intel HD Graphics 4600 version 10.18.10.3316

    * Windows 8.1 Pro 64 Bit

    * Yes.  We see this issue on all Intel graphics chips.  It is appears to be the way they are designed.

 dxdiag output attached.

Basically, if we DMA to an AMD chip we can do so in a linear way, but when we use an Intel chip there seems to be a non-linear mapping of the memory.  We're wondering if there is a way to configure the chip to use linear memory for DMA, or if there is any documentation explaining how the non-linear mapping works.

Mike