Register Spilling

[Biao_W_]

Hi, 

I am currently working on one OpenCL kernel with exhaustive register usage. I suspect the register spilling hinders the performance of my kernel on ivybridge. Using vtune amplifer I only get 10% EU activity. After searching around this forum, no post talking about register spilling. So my question is how could I confirm the bottleneck of one kernel is the register spilling. I compile the kernel and save the llvm IR, below is the IR code at the head of my kernel. Hope it help the supporter engineers shed some light to identify this problem.

  %1 = alloca i8 addrspace(1)*, align 8           ; <i8 addrspace(1)**> [#uses=4]
  %2 = alloca i8 addrspace(1)*, align 8           ; <i8 addrspace(1)**> [#uses=3]
  %3 = alloca i8 addrspace(1)*, align 8           ; <i8 addrspace(1)**> [#uses=3]
  %4 = alloca %struct.anon addrspace(1)*, align 8 ; <%struct.anon addrspace(1)**> [#uses=2]
  %5 = alloca %struct.anon addrspace(1)*, align 8 ; <%struct.anon addrspace(1)**> [#uses=2]
  %6 = alloca i16 addrspace(1)*, align 8          ; <i16 addrspace(1)**> [#uses=7]
  %7 = alloca i16 addrspace(1)*, align 8          ; <i16 addrspace(1)**> [#uses=2]
  %8 = alloca i32 addrspace(1)*, align 8          ; <i32 addrspace(1)**> [#uses=3]
  %9 = alloca i32 addrspace(1)*, align 8          ; <i32 addrspace(1)**> [#uses=3]
  %10 = alloca i32, align 4                       ; <i32*> [#uses=12]
  %11 = alloca i32, align 4                       ; <i32*> [#uses=3]
  %12 = alloca i32, align 4                       ; <i32*> [#uses=7]
  %13 = alloca i32, align 4                       ; <i32*> [#uses=4]
  %14 = alloca i32, align 4                       ; <i32*> [#uses=2]
  %15 = alloca i32, align 4                       ; <i32*> [#uses=2]
  %16 = alloca i32, align 4                       ; <i32*> [#uses=2]
  %17 = alloca i32, align 4                       ; <i32*> [#uses=2]
  %gidx = alloca i32, align 4                     ; <i32*> [#uses=5]
  %gidy = alloca i32, align 4                     ; <i32*> [#uses=6]
  %block = alloca i32, align 4                    ; <i32*> [#uses=2]
  %ref_num_offset = alloca i32, align 4           ; <i32*> [#uses=5]
  %list = alloca [2 x i32], align 4               ; <[2 x i32]*> [#uses=8]
  %ref_mb = alloca [2 x i32], align 4             ; <[2 x i32]*> [#uses=11]
  %output = alloca i8 addrspace(1)*, align 8      ; <i8 addrspace(1)**> [#uses=2]
  %frame_list_vector = alloca [2 x %struct.anon addrspace(1)*], align 8 ; <[2 x %struct.anon addrspace(1)*]*> [#uses=4]
  %frame_ref = alloca [2 x i8 addrspace(1)*], align 8 ; <[2 x i8 addrspace(1)*]*> [#uses=4]
  %localout = alloca i32, align 4                 ; <i32*> [#uses=15]
  %weight0 = alloca i32, align 4                  ; <i32*> [#uses=7]
  %weight1 = alloca i32, align 4                  ; <i32*> [#uses=5]
  %offset = alloca i32, align 4                   ; <i32*> [#uses=7]
  %buf_src_offset = alloca i32, align 4           ; <i32*> [#uses=5]
  %refn0 = alloca i32, align 4                    ; <i32*> [#uses=4]
  %refn1 = alloca i32, align 4                    ; <i32*> [#uses=4]
  %i = alloca i32, align 4                        ; <i32*> [#uses=11]
  %refn = alloca i32, align 4                     ; <i32*> [#uses=3]
  %list1 = alloca i32, align 4                    ; <i32*> [#uses=3]
  %weighted_offset = alloca i32, align 4          ; <i32*> [#uses=8]
  %weight = alloca i32, align 4                   ; <i32*> [#uses=4]
  %i2 = alloca i32, align 4                       ; <i32*> [#uses=8]
  %i4 = alloca i32, align 4                       ; <i32*> [#uses=7]
  %bit32WriteRow = alloca i32, align 4            ; <i32*> [#uses=3]
  %bit32WriteCol = alloca i32, align 4            ; <i32*> [#uses=3]
  %bit32WriteAddrLocal = alloca i32, align 4      ; <i32*> [#uses=2]
  %bit32WriteAddrGlobal = alloca i32, align 4     ; <i32*> [#uses=2]
  %outputin32bits = alloca i32 addrspace(1)*, align 8 ; <i32 addrspace(1)**> [#uses=2]
  %inputin32bits = alloca i32 addrspace(3)*, align 8 ; <i32 addrspace(3)**> [#uses=2]
  store i8 addrspace(1)* %reference, i8 addrspace(1)** %1
  store i8 addrspace(1)* %frame_list0_ref, i8 addrspace(1)** %2
  store i8 addrspace(1)* %frame_list1_ref, i8 addrspace(1)** %3
  store %struct.anon addrspace(1)* %frame_list0_vector, %struct.anon addrspace(1)** %4
  store %struct.anon addrspace(1)* %frame_list1_vector, %struct.anon addrspace(1)** %5
  store i16 addrspace(1)* %luma_weight, i16 addrspace(1)** %6
  store i16 addrspace(1)* %implicit_weight, i16 addrspace(1)** %7
  store i32 addrspace(1)* %ref_list_cpn, i32 addrspace(1)** %8
  store i32 addrspace(1)* %slot_table, i32 addrspace(1)** %9
  store i32 %log2_denom, i32* %10
  store i32 %use_weight, i32* %11
  store i32 %pic_width, i32* %12
  store i32 %pic_height, i32* %13
  store i32 %weighted_prediction, i32* %14
  store i32 %list_count, i32* %15
  store i32 %mb_stride, i32* %16
  store i32 %top, i32* %17

[Raghupathi_M_Intel]

On IVB there are 128 256-bit registers per EU thread. Unless you are using more than 128 per thread, I suspect spilling is the reason for the low EU activity. But I will forward this to the dev team.

Thanks,
Raghu