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AlderLake CPUID Leaf 0x18 and TLBs

TJW
Beginner
416 Views

I bought an Alderlake 12900K processor and I've been incorporating CPUID support for it into my tools. 

 

I wanted to investigate the TLB identification and detect in  your SDM CPUID documentation some possible issues.

 

On page 3-244 Vol 2A Table 3-12 for CPUID leaf 0x2 a byte return value of 0xFE which informs the user that leaf 0x18 reports the TLB structure for my Alderlake CPU.

 

Table 3-8 on page 3-229 describes how leaf 0x18 works.  I've pasted below what my processor returns for this leaf.  You can see what I decode those to be.  Inputing ECX = 0 I detect 9 (0-8) subleafs and the leaf for ECX = 0 is invalid.  So there are actually only 8 valid TLBs reported (in leafs 1-8).

Questions are below:

 

1. Intel has stated there's a 96 entry L1 DTLB for 4K pages but this processor only reports 64 entries for 4K, 32 for 2M/4M.  Can you explain why you say 96 entries?

 

2. In the Table 3-8 on page Vol 2A 3-230 it states for sub leafs with ECX >= 1 bits 0-4 of EDX identify the cache type of the TLB.  That said you are reporting bits set that exceed 00, 01, 10 and 11 in the lowest 2 bits and these are not documented as to the type of TLB.   For example in subleaf 3 EDX out: 00004125, so what is the cache type of this TLB?  In your documentations it says all other encodings are reserved.  I'm interpreting this as an error and assuming this encoding is a STORE ONLY TLB which your documentation is only valid for subleaf 0.  Can you help me understand this?

 

3. I'm detecting 2 shared (unified) TLBs.  Each has 1024 sets and can hold 4K pages but the first can also hold 2M/4M pages and the later can hold 1GB pages.  Is this correct?  If so then this matches the # of 4K page translations on Icelake (2048 entries).

 

 

 

 

 

leaf0x18_nsubleaf 8
EAX in: 00000018
ECX in: 00000000
EAX out: 00000008
EBX out: 00000000
ECX out: 00000000
EDX out: 00000000
EAX in: 00000018
ECX in: 00000001
EAX out: 00000000
EBX out: 00080001
ECX out: 00000020
EDX out: 00004022
translation cache type: Instruction TLB
tlb page type: 4K pages
associativity: 8
sets: 32
entries: 256
level: 1
maximum addressible IDs: 2
partitioning: 0

EAX in: 00000018
ECX in: 00000002
EAX out: 00000000
EBX out: 00080006
ECX out: 00000004
EDX out: 00004022
translation cache type: Instruction TLB
tlb page type: 2M/4M pages
associativity: 8
sets: 4
entries: 32
level: 1
maximum addressible IDs: 2
partitioning: 0

EAX in: 00000018
ECX in: 00000003
EAX out: 00000000
EBX out: 0010000f
ECX out: 00000001
EDX out: 00004125
translation cache type: Store Only TLB (fills ST ops)
tlb page type: 2M/4M/1G pages
associativity: 16
sets: 1
entries: 16
level: 1
maximum addressible IDs: 2
partitioning: 0

EAX in: 00000018
ECX in: 00000004
EAX out: 00000000
EBX out: 00040001
ECX out: 00000010
EDX out: 00004024
translation cache type: Load Only TLB (fills LD/ST ops)
tlb page type: 4K pages
associativity: 4
sets: 16
entries: 64
level: 1
maximum addressible IDs: 2
partitioning: 0

EAX in: 00000018
ECX in: 00000005
EAX out: 00000000
EBX out: 00040006
ECX out: 00000008
EDX out: 00004024
translation cache type: Load Only TLB (fills LD/ST ops)
tlb page type: 2M/4M pages
associativity: 4
sets: 8
entries: 32
level: 1
maximum addressible IDs: 2
partitioning: 0

EAX in: 00000018
ECX in: 00000006
EAX out: 00000000
EBX out: 00080008
ECX out: 00000001
EDX out: 00004124
translation cache type: Load Only TLB (fills LD/ST ops)
tlb page type: 1G pages
associativity: 8
sets: 1
entries: 8
level: 1
maximum addressible IDs: 2
partitioning: 0

EAX in: 00000018
ECX in: 00000007
EAX out: 00000000
EBX out: 00080007
ECX out: 00000080
EDX out: 00004043
translation cache type: Shared TLB
tlb page type: 4K/2M/4M pages
associativity: 8
sets: 128
entries: 1024
level: 2
maximum addressible IDs: 2
partitioning: 0

EAX in: 00000018
ECX in: 00000008
EAX out: 00000000
EBX out: 00080009
ECX out: 00000080
EDX out: 00004043
translation cache type: Shared TLB
tlb page type: 4K/1G pages
associativity: 8
sets: 128
entries: 1024
level: 2
maximum addressible IDs: 2
partitioning: 0

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3 Replies
AndrewG_Intel
Moderator
326 Views

Hello @TJW

Thank you for posting on the Intel® communities.


In order to make sure we have the proper information and we're on the same page, could you please provide confirm the following details?

1- What is your purpose with the investigation about "TLB identification" and "SDM CPUID documentation"? For instance, are you developing hardware or software using the Intel® Processor and Intel® tools? You mentioned that you "have been incorporating CPUID support for it into your tools". Please provide more details:

2- When you say TLB and DTLB, do you refer to "Translation Lookaside Buffer" and "Data Translation Lookaside Buffer"?

Also, when you say SDM CPUID, are you referring to "Intel® Smart Display Module"? If not, please elaborate more on the specific topis that you are referring to.

3- Could you please share links or references to the documentation regarding your comments and questions? If this is regarding private or confidential documents, please don't post them here in the thread and let us know so we can coordinate another option so you can provide this through a private communication method.


Best regards,

Andrew G.

Intel Customer Support Technician


AndrewG_Intel
Moderator
286 Views

Hello TJW

We are checking this thread and we would like to know if you need further assistance. Please do not hesitate to contact us back if you have additional inquiries.


Best regards,

Andrew G.

Intel Customer Support Technician


AndrewG_Intel
Moderator
257 Views

Hello TJW

We have not heard back from you so we will proceed to close this thread now. If you need any additional information, please submit a new question as this thread will no longer be monitored.


Best regards,

Andrew G.

Intel Customer Support Technician


Reply