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SMoha2
Beginner
1,724 Views

Architecture of IMCs(Integrated Memory Controllers) in latest Intel processors

I have been looking into Xeon architecture for a server application. I saw that Xeon supports Quad channel architecture with 3 DIMMs per channel. Following is a page from Intel's Xeon datasheet.

  • I have a doubt on the statement about DRAM controllers sharing a common address decode and DMA engine. If I have 4 cores on the Xeon processor, will I be able to access the 4 DDR channels simultaneously? For example can I use one CPU core to write to DDR channel 1 and another cpu core to read from DDR channel 2 simultaneously?
  • Also I assume the statement also means that I can have a DMA engine for a single channel at a time?

Appreciate any support.

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idata
Community Manager
194 Views

Hello electro_sm11,

Thank you for joining Processors community.

In order to address your inquiry, could you please let us know the Intel® Xeon® Processor you are interested? Also, please provide the specific datasheet where you got this statement.

Thank you.

Regards,

Amy C.

SMoha2
Beginner
194 Views

idata
Community Manager
194 Views

Thanks for the information.

Please let me double check this.

Regards,

Amy C.

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