We have a intel processor C3508 denverton ns series eval board. We are trying to develop coreboot image on it . It has 16 MB SPI boot flash .
Following are the things tried :
1. Downloaded 4.13 coreboot checkout . Built toolchain
2. Tried both changing native coreboot cache initialisation and FSP_T Initialsation .
3. Tried adding both micro_code generation from the tree and microcode_blob.h from the denverton package .
4. Added denverton fsp and including header files FSP*.h . (This step is not optional because , denverton series fsp's and header files are already checkedin in the coreboot code).
5. It generated coreboot.rom with the size 16MB . 67. Tried flashing coreboot.rom using dediprog tool . Programming is successful but no prints are coming .
6. Ram module is sodimm
In this some document it has mentioned to use spsFTIC tool to generate complete image .
We are not able to get any prints on this . Any help on this is highly appreciated .
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