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Hi,
We are using cyclone V (5CSEBA4U23I7N) in one of the project. Is it recommended to assemble the SOC in the first reflow process?. Is there any problem, if the SOC pass through the second reflow it includes DDR as well, in terms of reliability. We are following the lead free reflow process.
Thanks Regards
Binoy Johnson
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Hello, @Binoyjohnson
Thank you for posting on the Intel® communities.
For any issues, inquiries, documentation or license, please go to the Intel Community - FPGAs and Programmable Solutions and post your question on the appropriate subforum topic.
Thank you for your understanding.
Best regards,
Jocelyn M.
Intel Customer Support Technician.
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