Does Intel MMU really read CR3 to find a page entry?

[YCai]

I am developing a memory sharing tool, where my program needs to access the same memory block from different VAs.

I performed the following implementation on top of Linux 4.15:

  (1) allocate a memory block where the address is ensured to have the from: address 0xF100...ABC ; suppose that the 9 bits of 0x0F1 takes up the 1st entry of the PGD table;

 (2) calculate a new address 0xF200...ABC, and modify the 2nd entry of the PGD table to be have the same content as its 1st entry, indicating that the two addresses 0xF100...ABC and 0xF200...ABC can be mapped to the same memory block. 

According to my understanding, both address can be correctly accessed. For the second, as there is no cached entry in either TLB or other page-structure caches, MMU should walk through the page table based on CR3. The process will not cause a page fault, given that the first address can be correctly accessed.

However, the result on Intel CPU is that, when accessing the second address, a page fault is caused. It seems that CPU or MMU does not read CR3 to find the address; instead, it throws a page fault much earlier. 

So, I'd like to know that is the cause for the page fault (although a segmentation will be caused). How should I correctly implement the above idea on Intel CPU?

Thanks in advance.

[Esteban_D_Intel]

Hello YCai,

Thank you for posting on the Intel® communities.  

I was reviewing your post and I understand that you are developing a memory sharing tool. In order to provide you the appropriate support I would appreciate if you could provide the following information:

• To better assist you, please provide the model of the processor that is experiencing this behavior.
• Where is the processor installed? Please provide more details about the configuration/environment.
• Is it a specific processor family the one that is causing this behavior?

Esteban D.

Intel Technical Support Technician

[YCai]

Hi Esteban, 

Thanks a lot for your reply.

I include the required information below:

• CPU 1: Intel(R) Xeon(R) Gold 6148, on a Dell R740 PowerEdge server, with Ubuntu 18.04 x64 with Linux Kernel 4.15.0.1.
• CPU  2: intel core i7-7700HQ, on a Dell Precision 5520, with Ubuntu 14.04 x64 (also tried on Ubuntu 16.04c x64) with Linux Kernel 4.15.0.1 
• and some i5 models. 

Actually, we tested on different brands of x86-64 CPUs. But the implementation only failed on all tested Intel x86-64 CPUs. 

I am still working on this to find a feasible approach. I appreciate any of your suggestions.

Best regards,

YCai

[Esteban_D_Intel]

Hello YCai,

Thank you so much for your response.

After checkin the additional information provided and as you are the developer I would like to share with you the options that you have to get support on this matter.

First, If you have a FAE, I would strongly recommend to review this concern with your FAE for further recommendations.

Second,for product or technical inquiries, please submit your question on the Intel Resource & Design Center for Development for useful documentation and support.

As a third option, I would recommend contacting your local distributor. You can fin the list of Intel® Authorized Distributors here.

I hope that with the steps provided above you will be able to find the appropriate support on this matter and resolve your concern.

Esteban D.

Intel Technical Support Technician 

[Esteban_D_Intel]

Hello YCai, 

We hope that the information provided was helpful for you. If you need any additional information, please submit a new question as this thread will no longer being monitored  

Esteban D. 

Intel Technical Support Technician