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Does Intel(R) Xeon(R) Gold 6330 CPU implement TLB for sub-page-permission-table (SPPT) ?

cklzero
Beginner
917 Views

Hi, community,

I am interested in Intel EPT-Based Sub-page Write Protection (SPP), and I have done a simple performance evaluation on my CPU that supports SPP.

I did my test on Intel(R) Xeon(R) Gold 6330 CPU and based on Linux 5.7-rc5 patched by this patch (https://lwn.net/Articles/820748/). To my surprise, when I write 4-byte into the writable subpage (i.e.,  for the GPA, bit-1 (write access)  is cleared in EPT while bit 2S (S is bits 11:7 of the GPA in SPP vector is set to 1), it takes about 400 cycles for each write access. The result seems not reasonable.

 

Since the Linux trace event only catches some VM Exit caused by external interrupt rather than SPP, is it possible that the hardware does not implement TLB for SPPT? 

 

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13 Replies
Victor_G_Intel
Moderator
895 Views

Hello cklzero,


Thank you for posting on the Intel® communities.


Please let me review this information internally, and kindly wait for an update.


Once we have more information to share, we will post it on this thread.


Regards,


Victor G.

Intel Technical Support Technician 


Victor_G_Intel
Moderator
835 Views

Hello cklzero,


Thank you for your patience.


Please allow us some more time with this inquiry. We are investigating this internally with our engineering team and we will be updating the thread within a week from now.


Regards,


Victor G.

Intel Technical Support Technician 


Victor_G_Intel
Moderator
787 Views

Hello cklzero,

 

Thank you for your patience.

 

Based on your situation, and according to our engineering department, though the Xeon 6330 has more cores, the Xeon 6226R has a higher base frequency.

 

If we assume an application can use all available cores and those cores run at the base frequency and no other impact on performance by other platform factors (i.e., BIOS settings, CPU utilization, no memory bandwidth being a bottleneck, etc.), we can calculate as an example the following:

 

Using the 6230 SKU, 20 cores each running at 2.1GHz = 20 * 2.1 = 42GHz worth of execution

 

Using the 6226R SKU, 16 cores each running at 2.9GHz = 16 * 2.9 = 46.4GHz worth of execution

 

So, in the same amount of time, the 6226R can execute more instructions than the 6230. This likely explains the better performance seen with the 6226R than the 6230.

 

Please let us know if you have any doubts about the information provided.

 

Regards,

 

Victor G.

Intel Technical Support Technician 

 

cklzero
Beginner
708 Views

Hi, Victor,

 

Thank you for your reply.

 

However, it seems the answer to another question. In short, my question is that whether the 6330 CPU uses the Translation Lookaside Buffer (TLB) to accelerate sub-page-permission-table (SPPT) translation.

cklzero
Beginner
774 Views

Hi, Victor,

 

Thank you for your reply.

 

However, it seems the answer to another question. In short, my question is that whether the 6330 CPU uses the Translation Lookaside Buffer (TLB) to accelerate sub-page-permission-table (SPPT) translation.

Victor_G_Intel
Moderator
692 Views

Hello cklzero,


Thank you for your response.


We are still investigating this matter with our engineering team and we will be updating the thread as soon as possible.


Regards,


Victor G.

Intel Technical Support Technician 


Victor_G_Intel
Moderator
530 Views

Hello cklzero,


Thank you for your patience.


In order to continue with our investigation, we would like to ask if it’s possible for you to share a copy of your testing app with us?


Regards,


Victor G.

Intel Technical Support Technician


Victor_G_Intel
Moderator
460 Views

Hello cklzero,


Were you able to check the previous post?   


Please let me know if you need further assistance.   


Victor G.  

Intel Technical Support Technician  


cklzero
Beginner
431 Views

Hi Victor,

 

I'm sorry that I forgot to check my email these days. The attachment is my testing program spp_perf_test.c and how I use the testing program.

Victor_G_Intel
Moderator
425 Views

Hello cklzero,


Thank you for your response.


Please let us review this testing program internally with our engineering team and kindly wait for an update. We appreciate all the effort and willingness from your end.


Once we have more information to share, we will post it on this thread.


Regards,


Victor G.

Intel Technical Support Technician 


JoseH_Intel
Moderator
397 Views

Hello cklzero,


We want to inform that we are actively working on your question. Also we would like to know for which company are you working with?


We will look forward to your updates.


Regards


Jose A.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit:

https://intel.com/support/serverbios


cklzero
Beginner
376 Views

Hi Jose,

 

I'm still a graduate student and not working for any company now. SPP is used in my research project, so that I want to know its performance.

 

Victor_G_Intel
Moderator
372 Views

Hello cklzero,


Thank you for your response.


Once we have more information to share, we will post it on this thread. Thank you again for the information provided so far and for your patience.


Regards,


Victor G.

Intel Technical Support Technician


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