[Eagle Stream][SPR] How to enable OS access to SPD controller?

[BoyceHong]

Hello there,

I am going to develop a linux tool to access DDR5 SPD for SPR processor, but now I can not write the registers of SPD controller. For example:

SPR EDS Vol2, UBOX/I3C Memory Mapped I/O Registers/COMMAND_QUEUE_PORT

This register only support OS read access, how to enable this? I don't find the policy control registers.

Thanks,

Boyce

[Victor_G_Intel]

Hello BoyceHong,

Thank you for posting on the Intel® communities.

In this case, we need to inform you that through this channel we don't provide support for unreleased products.

However, you still have two options to receive the support that you need you can either contact the field application engineer (FAE) that Intel assigned to your project, or you are also welcome to contact our developer team by following the instructions in the link below.

How to Create a Support Request at the Online Service Center

https://www.intel.com/content/www/us/en/developer/articles/troubleshooting/how-to-create-a-support-request-at-online-service-center.html

Important note: For future interactions in the forum please remember that there is no need to create multiple threads on the same topic/request. We have deleted the second thread that you created to avoid any confusion and duplicated responses.

Regards,

Victor G.

Intel Technical Support Technician  

[SergioS_Intel]

Hello BoyceHong,

We are following your case and would like to know if you have any additional questions or if we can close this thread.

Regards,

Sergio S

Intel Technical Support Technician