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11838 Discussions

Hardware Performance counters vs Uncore Performance Counters

aozcan
New Contributor I
600 Views

Hi,

 

What separates uncore performance counters from hardware performance counters? Is there a coined term "software performance counters" for Intel microarchitectures?

Suppose that I want to measure LLC victims on a specific state (M, E, S or F) on a Skylake microarchitecture. As far as I understand, I can do this with:

1) Hardware performance counters (using UNC_CHA_LLC_VICTIMS event)

https://perfmon-events.intel.com/

2) Uncore performance counters

https://kib.kiev.ua/x86docs/Intel/PerfMon/336274-001.pdf

 

If my understanding is correct, what is the point of having 2 distinct way of measuring the same event? Are there any differences between the 2 way?

 

Edit: my server is Skylake.

 

Thanks

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1 Solution
SergioS_Intel
Moderator
389 Views

Hello aozcan,


Thank you for waiting for our updates.


Performance counters covered by (1) are a superset of (2).


Document (1) covers all the performance counters available (core and uncore), and document (2) explains the “uncore” side of the performance counters to focus more on the LLC and the uncore interconnect.


Basically, they are the same.

 


“uncore” == LLC + interconnect + memory controller + IO



(1) is Hardware performance counters (using UNC_CHA_LLC_VICTIMS event) https://perfmon-events.intel.com/ 


(2) is Uncore performance counters https://kib.kiev.ua/x86docs/Intel/PerfMon/336274-001.pdf 



Please let us know if you need further assistance.


Best regards,

Sergio S.

Intel Customer Support Technician


For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios


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6 Replies
SergioS_Intel
Moderator
569 Views

Hello aozcan,


Thank you for contacting Intel Customer Support.

 

In order to better assist you, can you please provide us the model of your server and also the model of your Intel(R) processor?


We will be looking forward to your response.


Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios


SergioS_Intel
Moderator
536 Views

Hello aozcan,

 

We are following your question and would like to know if you were able to gather the information that we requested in our previous post.

 

We will be looking forward to your response.

 

Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios

 

aozcan
New Contributor I
513 Views

This is lscpu output:

 

Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 18
On-line CPU(s) list: 0-17
Thread(s) per core: 1
Core(s) per socket: 18
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 85
Model name: Intel(R) Xeon(R) Gold 6154 CPU @ 3.00GHz
Stepping: 4
CPU MHz: 3699.829
CPU max MHz: 3700.0000
CPU min MHz: 1200.0000
BogoMIPS: 6000.00
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 1024K
L3 cache: 25344K
NUMA node0 CPU(s): 0-17
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb cat_l3 cdp_l3 invpcid_single intel_ppin intel_pt ssbd mba ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts pku ospke md_clear spec_ctrl intel_stibp flush_l1d

SergioS_Intel
Moderator
488 Views

Hello aozcan,


We appreciate the additional information, please allow us to check it and we will get back to you.


Best regards,

Sergio S.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios



JoseH_Intel
Moderator
466 Views

Hello aozcan,


Just wanted to let you know that this might take a while to look into but we will provide an update by next week. Thank you for understanding.


Regards


Jose A.

Intel Customer Support Technician

For firmware updates and troubleshooting tips, visit:

https://intel.com/support/serverbios



SergioS_Intel
Moderator
390 Views

Hello aozcan,


Thank you for waiting for our updates.


Performance counters covered by (1) are a superset of (2).


Document (1) covers all the performance counters available (core and uncore), and document (2) explains the “uncore” side of the performance counters to focus more on the LLC and the uncore interconnect.


Basically, they are the same.

 


“uncore” == LLC + interconnect + memory controller + IO



(1) is Hardware performance counters (using UNC_CHA_LLC_VICTIMS event) https://perfmon-events.intel.com/ 


(2) is Uncore performance counters https://kib.kiev.ua/x86docs/Intel/PerfMon/336274-001.pdf 



Please let us know if you need further assistance.


Best regards,

Sergio S.

Intel Customer Support Technician


For firmware updates and troubleshooting tips, visit :https://intel.com/support/serverbios


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