High impact of c++ atomic operations on cpu utilization of Ice Lake.

[Sashahd]

Hi,

  Our application uses c++ atomic definitions and actions to synchronize shared memory  counters between cores:

  std::atomic_uint_fast64_t packetCounter;

  std::atomic_uint_fast64_t byteCounter;

One core accumulates and resets counters by packetCounter.exchange(..) and byteCounter.exchange(..).

  Other cores only increment counters.

  We used this system on Intel E5-2690v2 (Ivy Bridge) and haven't observed sensible cpu utilization influence.

  On our new platform using Intel 6330N (Ice Lake), cpu utilization of the task which is accumulating and resetting these counters raised in 10 times.

  We've used same 19 cores (in one task is making accumulating and resetting and in other 18 only tasks incrementing counters) on both devices to make fair compare. The same executable was tested on both devices.

  Is anyone aware of this issue, related to Ice Lake ?

May be there is some config parameters which we have missed ?

Thanks,

   Sasha

[Victor_G_Intel]

Hello Sashahd,

Thank you for posting on the Intel® communities.

To continue with this request of assistance, would you mind providing us with the following information:

1. Model of the motherboard/motherboards where both processors were tested?
2. Can you please provide more details about what your app is intended to do?
3. Please provide as many details about the app as possible: name, release date, meta platforms, links.
4. Please provide the operating system’s name and build being used with both processors during your tests.
5. Did you obtain these processors from one of the authorized distributors?

I look forward to hearing from you.

Regards,

Victor G.

Intel Technical Support Technician

[Victor_G_Intel]

Hello Sashahd,

Were you able to check the previous post?  

Please let me know if you need further assistance.  

Best regards,

Victor G. 

Intel Technical Support Technician

[Victor_G_Intel]

Hello Sashahd, 

We have not heard back from you. 

If you need any additional information, please submit a new question as this thread will no longer be monitored  

Regards,

Victor G.  

Intel Technical Support Technician