I want to solve 'top level design entity is undefined' problem. Please help me.

[Austin_7]

I'm the student and the beginner at FPGA.  I found some people who had the same problem. I think I checked  what they did, but the problem still exists. Please help me. I uploaded one minute video. Sorry for bad English because I'm Korean student. But you can see the window and it may help you to find the problem. I also uploaded the file.

I really hope you to help me.

Thank you.

[Austin_7]

I rewrite the question in another category. I want to remove it, but I don't know how to do it. Let me know it.

[DeividA_Intel]

Hello Austin_7,  

Thank you for posting on the Intel® communities.   

I could see that we have created another thread where you are getting support, please kindly refer to that thread for more assistance.

Do not worry about this post, I will proceed to close this thread to avoid duplication and the support will continue on your second thread/post. 

Regards,  

Deivid A. 

Intel Customer Support Technician