Hi Vladislav0504,
Intel® Fast Memory Access Technology was developed for the Graphics Memory Controller Hub (GMCH) backbone architecture that improves system performance by optimizing the use of available memory bandwidth and reducing the latency of the memory accesses.
Current Intel® Xeon® Scalable Processors do not include graphics controllers.
Intel has changed the Cache Hierarchy.
In the previous generation, the mid-level cache was 256 KB per core and the last level cache was a shared inclusive cache with 2.5 MB per core. In the Intel Xeon processor Scalable family, the cache hierarchy has changed to provide a larger MLC of 1 MB per core and a smaller shared non-inclusive 1.375 MB LLC per core. A larger MLC increases the hit rate into the MLC resulting in lower effective memory latency and also lowers demand on the mesh interconnect and LLC. The shift to a non-inclusive cache for the LLC allows for more effective utilization of the overall cache on the chip versus an inclusive cache.
More technical details at Intel® Xeon® Processor Scalable Family Technical Overview.
https://software.intel.com/en-us/articles/intel-xeon-processor-scalable-family-technical-overview
Regards,
Miguel C
Intel Customer Support
