Is ARM Cortex A9 in Cyclone V support Backgorund memory access through Debug Access port?

[EBERLAZARE_I_Intel]

Hi,

By background memory access, do you mean to access the memory during runtime?

[MZuba3]

yes, I want to use Segger J-link Jtag with RTT for logging. Does it support memory access during runtime?

[EBERLAZARE_I_Intel]

Hi,

 To debug the HPS External Memory Interface, you can change the settings inside the preloader software to enable Runtime Calibration Report and Debug Level info.

More info on this, please check the "using the Preloader To Debug the HPS SDRAM" section here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-cv-av-soc-ddg.pdf#page=64