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Is there any ideal condition where rtm will never fail?

Alam__Shariful
New Contributor I
206 Views

I know that there are many reasons for rtm to fail and the successful commit of code block inside rtm is not guaranteed. I was wondering if there is any ideal condition where rtm will always commit successfully when running a large segment of code? 

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3 Replies
Alberto_Sykes
Employee
178 Views

Alam__Shariful, Thank you for posting in the Intel® Communities Support.


In order for us to be able to provide the most accurate assistance on this matter, we just wanted to confirm a few details:

Are you a developer?

Are you working on a project?

What is that project about, hardware or software?

When you mentioned, RTM, do you refer to Restricted Transactional Memory?

What is the model of the Intel® Processor that you are referring to?


Any questions, please let me know.


Regards,

Albert R.


Intel Customer Support Technician

A Contingent Worker at Intel


Alam__Shariful
New Contributor I
176 Views

Hi Mr. Albert,

Thanks for your reply. following are my answer to your question,

  • Are you a developer?
    • No. I'm a security researcher.
  • Are you working on a project?
    • Yes, I'm working on a research project.
  • What is that project about, hardware or software?
    • This project is about software security
  • When you mentioned, RTM, do you refer to Restricted Transactional Memory?
    • Yes, by RTM I mean Restricted Transactional Memory
  • What is the model of the Intel® Processor that you are referring to?
    • I have an intel skylake processor. My cpuinfo shows the following,
    •  

 

$ cat /proc/cpuinfo 
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 94
model name	: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz
stepping	: 3
microcode	: 0xdc
cpu MHz		: 799.929
cache size	: 8192 KB
physical id	: 0
siblings	: 8
core id		: 0
cpu cores	: 4
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 22
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb invpcid_single intel_pt ssbd ibrs ibpb stibp kaiser tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx rdseed adx smap clflushopt xsaveopt xsavec xgetbv1 dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp md_clear flush_l1d
bugs		: cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs taa itlb_multihit srbds
bogomips	: 6814.26
clflush size	: 64
cache_alignment	: 64
address sizes	: 39 bits physical, 48 bits virtual
power management:

 

Alberto_Sykes
Employee
153 Views

Hi Alam__Shariful, You are very welcome, thank you very much for providing that information.


In this case, to gather the information that you are looking for, please visit, sing-in and submit your inquiry on our Intel® Resource and Design Center web site, you will receive further peer to peer assistance on this topic in there:

https://www.intel.com/content/www/us/en/design/resource-design-center.html


Regards,

Albert R.


Intel Customer Support Technician

A Contingent Worker at Intel


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