KBLU i3-7100u/i5-7200 can support below the instruction set ???

[JPan3]

​ The processor must meet the following requirements: 

1. CMPXCHG16b 

2. PrefetchW 

3. LAHF / SAHF

[Wanner_G_Intel]

Hello JPan3, Both Intel® Processors support CMPXCHG16B instruction set. We will get back to you as soon as we have more information about PrefetchW and LAHF / SAHF. Wanner G. Intel Customer Support Technician Under Contract to Intel Corporation

[Wanner_G_Intel]

Hello JPan3, I would like to add that all Intel Core i7, i5, or i3 processors, as well as all Pentium or Celeron processors based on the Clarkdale, Arrandale, Sandy Bridge, or newer microarchitectures, support these features, as well as Intel® Atom and Celeron Silvermont processors. -The CMPXCHG16B instruction performs an atomic compare-and-exchange on 16-byte values. It is supported on all modern x86-64 processors. -The PREFETCHW instruction is a hint to the processor to prefetch data from memory into the cache in anticipation for writing. It is supported on all modern x86-64 processors succeeding Nehalem. -The LAHF and SAHF load and store the contents of the AH register into the flags register, respectively. Some older Intel® processors without hardware virtualization (VT-x) functionality do not support this instruction when running in 64-bit long mode; these are mostly limited to certain low-end processors predating Nehalem. Wanner G. Intel Customer Support Technician Under Contract to Intel Corporation

[Wanner_G_Intel]

Hello JPan3, Were you able to review the information posted above? Wanner G. Intel Customer Support Technician Under Contract to Intel Corporation