Processors (Intel® Core™, Intel® Xeon®, etc); processor utilities and programs (Intel® Processor Identification Utility, Intel® Extreme Tuning Utility, Intel® Easy Streaming Wizard, etc.)
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L1 to L1 in Quad-Core


I am using a Xeon E5405 (BX80574E5405A) Quad-Core and I am trying to figure out how L1-cache is managed between cores.


More precisely, what happens when two cores have a copy of the same data in their respective L1-cache and that one of the two cores writes to that data ?


1 - in the case of two cores of the same pair (does it trigger a L1-miss at the next "read" in the second core ?)


2 - in the case of two cores of a different pair (does it trigger an avalanche of L1-miss, L2-miss between the core pairs ?)

The same question can be put to the equivalent situation between the L2-cache of the two core-pairs in the Quad-Core.

(does a write-back from L1 to L2 in the first core-pair trigger a L2-miss and L1-miss at the next "read" in the second core-pair ?)

(in the same order of things, is there a direct communication through the FSB between L2's of both core-pair in the Quad or those data have to transit by the RAM ?)



Some insight on this would be greatly appreciated.



Best regards,



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