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L2 Cache-Partitioning Support in Intel Raptor Lake processor (Intel(R) Core(TM) i9-13900K)

osdeveloper
Novice
1,671 Views

Hi,

After obtaining promising research-related results with L2 cache-partitioning support (L2CAT) in an Alder Lake processor (Intel(R) Core(TM) i9-12900K), we purchased a system featuring an Intel(R) Core(TM) i9-13900K "Raptor Lake" processor. Unfortunately, this new processor does not apparently have the "l2cat" capability, and we are unable to run any kind of experiments with L2 CAT.  

We are using GNU/Linux Debian v11, with a recent Linux Kernel v6.2.4. This is the output of the lscpu command:

osdeveloper@raptor2:~$ lscpu 
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
Address sizes: 46 bits physical, 48 bits virtual
CPU(s): 24
On-line CPU(s) list: 0-23
Thread(s) per core: 1
Core(s) per socket: 24
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 183
Model name: 13th Gen Intel(R) Core(TM) i9-13900K
Stepping: 1
CPU MHz: 800.000
CPU max MHz: 5800.0000
CPU min MHz: 800.0000
BogoMIPS: 5990.40
Virtualization: VT-x
L1d cache: 1.1 MiB
L1i cache: 768 KiB
L2 cache: 48 MiB
L3 cache: 36 MiB
NUMA node0 CPU(s): 0-23
Vulnerability Itlb multihit: Not affected
Vulnerability L1tf: Not affected
Vulnerability Mds: Not affected
Vulnerability Meltdown: Not affected
Vulnerability Mmio stale data: Not affected
Vulnerability Retbleed: Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2: Mitigation; Enhanced IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Not affected
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constan
t_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse
3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault invpcid_
single ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid rdseed adx smap
clflushopt clwb intel_pt sha_ni xsaveopt xsavec xgetbv1 xsaves split_lock_detect avx_vnni dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_
pkg_req hfi umip pku ospke waitpkg gfni vaes vpclmulqdq tme rdpid movdiri movdir64b fsrm md_clear serialize pconfig arch_lbr ibt flush_l1d arch_capabilities

 

The platform integrates a GigaByte Z790UD Motherboard, whose BIOS has just been updated to its latest version (from June 2023). We could not find any option in the BIOS to enable/disable L2Cat.

I am aware of the Linux-related issues with L2 CAT in Alder Lake processors --as explained in this Intel document --, but our BIOS does not feature a L2 QOS Enumeration entry or similar to the one mentioned in the document.

Does this processor (Intel(R) Core(TM) i9-13900K) really support L2Cat, or Is this feature not being correctly enabled/enumerated due to a BIOS issue?

Thank you very much in advance!

Regards

 

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10 Replies
Alberto_R_Intel
Employee
1,636 Views

osdeveloper, Thank you for posting in the Intel® Communities Support.


We will be more than glad to assist you with this matter. 


In reference to your inquiry, in order for us to provide the most accurate assistance on this subject, I will do further research on this matter. As soon as I get any updates, I will post all the details on this thread.


Any questions, please let me know.


Regards,

Albert R.


Intel Customer Support Technician


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osdeveloper
Novice
1,611 Views

Thank you, Albert.

 

I look forward to receiving your response.

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Alberto_R_Intel
Employee
1,572 Views

Hello osdeveloper, You are very welcome, I just received an update on this matter.


After reviewing the case, we can see in the documents that you provided, that to get L2CAT supported, the 12th Generation SKUs shown are actually for embedded processors only, see page 7.

 

In this section:

2.8 L2 Cache Allocation Technology (CAT)

12th Generation Intel® Core™ processor systems with a BIOS that supports Intel® Time Coordinated Computing (Intel® TCC) will have a BIOS option to enable enumeration of L2 Cache Allocation Technology.

 

As the 13th generation is having the same hybrid architecture as the 12th generation, the requirement should be the same. So, in this scenario, what we recommend as the next thing to do will be to get in contact back with the motherboard vendor and ask them why the “L2 QOS Enumeration” option in BIOS is not available. If by any chance, it is not available from the motherboard vendor, then that will mean it is not supported.


Regards,

Albert R.


Intel Customer Support Technician



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Andres_Intel
Employee
1,530 Views

Hello osdeveloper,

 


Were you able to contact back the motherboard vendor and ask them why the “L2 QOS Enumeration” option in BIOS is not available?


Let us know if you still need assistance.

 


Best regards, 


Andres P.

Intel Customer Support Technician


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osdeveloper
Novice
1,516 Views

Hi Andres and Albert,

 

Thank you very much for your help! I will contact the motherboard vendor as soon as possible, and will post a message in this thread as soon as I have a response.

 

Best regards

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Andres_Intel
Employee
1,489 Views

Hello osdeveloper,

 


Thank you for your response and for keeping me informed.


I will be waiting for your response.

  


Regards,


Andres P.

Intel Customer Support Technician


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Andres_Intel
Employee
1,451 Views

Hello osdeveloper, 



Do you have any updates from the motherboard vendor?

Let us know if you still need assistance.



Best regards,


Andres P.

Intel Customer Support Technician


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Alberto_R_Intel
Employee
1,423 Views

Hello osdeveloper, Since we have not heard back from you, we are closing the case, but if you have any additional questions, please post them on a new thread so we can further assist you with this matter.


Regards,

Albert R.


Intel Customer Support Technician


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osdeveloper
Novice
1,407 Views
Hi Andres and Alberto,
 

Sorry for the delay. I have just opened a detailed ticket on the motherboard vendor's support site. For that I needed to gather information that required physical access to the computer; that took me a while.

I will post a message in this thread as soon as I have a response.

Best regards

 

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osdeveloper
Novice
1,364 Views

Hi,

Gygabyte just informed us that their Z790UD Motherboard does not support the "L2 QoS Enumeration" option. So, it looks like we have no other choice but to purchase another motherboard.

Do you happen to know of any motherboard that currently support this feature? We are finding it hard to identify a motherboard that actually supports this, just by looking at the public specs and documentation provided by the various motherboard vendors. Perhaps, this has to do with the fact that l2cat is probably not a feature required by the average user...

Best regards, and again, thank you very much in advance for your help.

 

 

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