I recently read this article from Intel: https://software.intel.com/en-us/articles/optimizing-computer-applications-for-latency-part-2-tuning... Optimizing Computer Applications for Latency: Part 2: Tuning Applications | Intel® Software .
I'm trying to configure my system for low latency applications.
My processor is a Xeon E5-2687W v4, and the tests from the article were done on a E5-2697 v2. I believe I have a higher spec processor than the one used in the article, so I would expect to see better timings when I run the test on my machine.
I configured the kernel and BIOS as the article indicated. I built the spsc test program on my box (also tried it with compiler optimizations enabled). My test case is using a single NUMA node:
Avg lat = 0.120415, Avg lat w/o outliers = 0.105183, lowest lat = 0.044998, highest lat = 524.493359, outliers = 336
Stdev = 0.000835, stdev w/o outliers = 0.001248
I'm seeing 105 nanos for the average case compared to 67 nanos in the article. Is this difference attributable to difference in processor spec? Any help to resolve the difference would be greatly appreciated!
Thank you for contacting Intel® Communities Support.
My best recommendation is to contact your Linux Distribution.
You can check the Technical Resources for Designers, Engineers, and Developer https://www.intel.com/content/www/us/en/design/resource-design-center.html?_ga=2.87657183.610584200.... here.
Intel Developer zone https://software.intel.com/en-us/home here.
Also you can contact the Field Application Engineer with our Intel Authorized Distributors http://locate.intel.com/ here.