Order of stores to main memory

[idata]

I have asked a similar question earlier that has remained unanswered.

Let me ask a simpler question here:

Is there any way to establish "an" order for stores reaching the main memory for xeon processors?

Let's say I use uncached (strongly uncached) mode and use stores (MOVs or MOVNTs) and have access to flush (CLFLUSH) and memory sync and whatever else you can think of.

I do the following in my code:

Store to location A1

Store to location A2

...

Store to location An

Store to location B

Is there ANY METHOD (using special aching mode, using msync, flushes, etc) which I can use to make sure that the last store (to location B) gets to the main memory after all previous stores to A1, A2, ..., and An?

The answer could be a simple NO (that I would like to know for sure) but if the answer is YES, then how?

Any help is much appreciated.

Thanks.