I think there might be a slight error in figures 2-1 and 2-2 of the Intel Software Development Manual Volume 3: System Programming Guide.
Figures 2-1 and 2-2 depict an overview of the System-Level Registers and Data Structures for IA-32 and IA-32e mode, respectively. At the top of the figure, there's a legend specifying that physical addresses are denoted by dotted-line arrows:
At the bottom of the figures, the data structures for the memory-management unit can be seen in an page mapping example.
Given that the Page-Structure entries contain the physical address of the next-level page structure (or a mapped page frame, in the case of Page Table Entries), those arrows should be denoted by dashed-line arrows (Physical Address).
See the following pictures:
The highlighted arrows should be of the same kind as the arrow that goes from the CR3 to the Page Directory or PML4 in figures 2-1 and 2-2 respectively.
In chapter 4.2 "HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW", it is mentioned that indeed, those entries contain physical addresses:
"Each paging-structure entry contains a physical address, which is either the address of another paging structure or the address of a page frame. In the first case, the entry is said to reference the other paging structure; in the latter, the entry is said to map a page."
charco, Thank you for posting in the Intel® Communities Support.
Thank you very much also for providing those details, for this specific matter to be addressed, what we recommend is visit, sign-in and submit your comments in our Intel® Developer Zone of in our Intel® Resource and Design Center web sites:
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Intel Customer Support Technician
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Thank you for your reply.
Could you point me to where I should post the comments? I followed the links and tried to look for a place to post comments to, I get redirected to community.intel.com (this web page).