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KKuro3
Beginner
976 Views

Problems with enabling TPH on Intel Xeon E5-2630 v3 platform

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Hello everyone! I am RTL designer and i'm developing network adapter. I've discovered in PCIe spec feature called TPH that allows PCIe endpoint device to put transactions directly into CPU cache. According to specification i've set all necessary flags and fields in TLP header in outgoing packets (I've set TH flag = 0x1, PH field = 0x2). However i still have open question what steering tag value should be. From what i undestand it is simply a node ID, and as i have 2-socket platform it can be 0x0 or 0x1. I've tested this feature and measured round-trip latency and saw no perfomance gain from it. So i think i simply didn't switch on this capability properly. My question is: what else (in addition to enabling it on my PCIe EP device) i need to do to enable TPH on Intel Xeon E5-2630 v3 platform?

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KKuro3
Beginner
54 Views

I've figured it out. On Intel Xeon E5-2630 v3 platform all writes from PCIe endpoints already are redirected to cache. Thanks for DDIO technology. No hardware support such as TPH is needed.

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KKuro3
Beginner
55 Views

I've figured it out. On Intel Xeon E5-2630 v3 platform all writes from PCIe endpoints already are redirected to cache. Thanks for DDIO technology. No hardware support such as TPH is needed.

View solution in original post