Questions abount HBM details in Sapphire Rapid

[oleotiger1]

I have a few questions about HBM in Sapphire Rapid series CPUs.

1. Why is  HBM organized as a direct-mapped cache in cache mode? Why not full-associative or set-associate?
2. What is the granularity of the cache line of HBM in cache mode? Why was this granularity chosen? Can it be made dynamic like a transparent huge page in the OS? Why or why not?
3. Is there any public documentation detailing how HBM works?

[IntelSupport]

Hi Oleotiger1,

Thank you for posting on Intel community forum.

Please note we are reviewing the queries related to HBM.

Meanwhile, we request to refer the below links related to HBM.

https://www.intel.com/content/www/us/en/content-details/762142/video-high-bandwidth-memory-hbm-configuration.html?wapkw=HBM

https://www.intel.com/content/www/us/en/developer/articles/technical/qcd-performance-optimization-with-hbm.html?wapkw=HBM#gs.0okxsv

https://www.intel.com/content/www/us/en/content-details/762147/video-high-bandwidth-memory-hbm-overview.html?wapkw=HBM

Regards,

Megha

[IntelSupport]

Hi Oleotiger1,

Thank you for posting on Intel Community.

Please be informed for the queries related to HBM in Sapphire Rapid series CPUs we request you to refer the below Resource and document center link.

https://www.intel.com/content/www/us/en/developer/programs/overview.html#gs.74xo6e

Please sign-up for Developer Zone for further assistance.

Regards,

Megha

[Meghak]

Hi Oleotiger1,

Thank you for posting on Intel Community.

Please let us know if the issue reported is resolved.

Best Regards,

Megha

[Meghak]

 Hi Oleotiger1,

Thank you for posting on Intel community.

We have not received a reply from you , and as such, we will be closing your chat.

If you want to continue support, please reply to this email and we will reopen your chat or create a new one so that we can continue to support you.

Best Regards,

Megha k