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Hello all
We are developing new platform based on Tiger Lake processor. We reference our design much from TGL UP4 LPDDR4 AEP design. But we notice that our platform not always de-assert PLTRST#, even though we've already assert PCH_PWROK and SYS_PWROK. In fact, it took us like more than 10 times plug in and plug out battery to de-assert PLTRST#.
We don't know what we're misconfigure or hardware-relate problem. Can you please give me advice how to solve this problem? Lots of thanks in advance!
Jon
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Hello Jon-xelex
Thank you for your patience in this matter.
After checking this further, for scenarios like this one when building a system, you will need help through a different channel of support since your Hardware Design inquiries will require a closer look by an Intel Field Application Engineer (FAE) or submit the issue through Intel® Premier Support (IPS).
Note:
Your company's Purchasing Department will normally have your Intel representative's contact information for an FAE. If you do not have a contact, you may want to speak with a Field Application Engineer from a local distributor to see whether they are able to help. A list of Intel® Authorized Distributors can be found here.
Best regards,
Andrew G.
Intel Customer Support Technician
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Hello @Jon-xelex
Thank you for posting on the Intel® communities.
We understand that you are developing a new platform based on the Tiger Lake UP4 processor. Just to make sure we have the proper details about your environment and provide you with the proper information, could you please confirm the exact model(s) of the Tiger Lake Processors that are related to this request?
Also, when you said you are developing a new platform, do you mean you are building a system or motherboard or similar device? Please provide details.
Best regards,
Andrew G.
Intel Customer Support Technician
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Hello Andrew,
I'll provide some detail information here:
- We used Intel Core 1180G7 (QS)
- We develop a 2-in-1 platform which we referenced design from Tiger Lake UP4 LPDDR4 AEP
Best regards,
Jon
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Hello Jon-xelex
Thank you for the details. Please allow us to review this and we will be posting back in the thread as soon as more information is available.
Best regards,
Andrew G.
Intel Customer Support Technician
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Hello Andrew
I want to add some extra information: our board also suffer from situation that it will try to reinitiate boot up 3 times (by assert then de-asserted SLP_S3#). If 4th time does not de-assert PLTRST# then it will hang. It seems like we suffer from sighting ID #22010323072. We double check PMC FW version and it passed the required PMC FW version 1020 which fix issue #22010323072.
Interestingly, in sighting ID #22010323072 Intel state that root cause was VCCST logic and "Designs which do not have VCCST Power Gate, will require system dependent solution". Can you please clarify what is power gate of VCCST, and what is system dependent solution?
solution
Best regards
Jon
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Hello Jon-xelex
Thank you for your patience in this matter.
After checking this further, for scenarios like this one when building a system, you will need help through a different channel of support since your Hardware Design inquiries will require a closer look by an Intel Field Application Engineer (FAE) or submit the issue through Intel® Premier Support (IPS).
Note:
Your company's Purchasing Department will normally have your Intel representative's contact information for an FAE. If you do not have a contact, you may want to speak with a Field Application Engineer from a local distributor to see whether they are able to help. A list of Intel® Authorized Distributors can be found here.
Best regards,
Andrew G.
Intel Customer Support Technician
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Hello Jon-xelex
We will proceed to close this thread now. If you need any additional information, please submit a new question as this thread will no longer be monitored.
Best regards,
Andrew G.
Intel Customer Support Technician
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Hi Jon-xelex,
Have you already solved this problem? could you help to share the solution?

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