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12775 Discussions

Typical SSE or Extra Registry Bit Configuration?

SM-1234
Novice
343 Views

Forget my own out-of-support CPU processor, then, and presume some hypothetical, most "up-to-date" 64 bit one, that intel knows most Desktop Windows PC's most have, as of now, 2022, can that be picked and reapplied to the same questions.

1)  I had thought that floating point binary digits are written and dealt with entirely inside the floating point unit of the 'Modern CPU'.  Is this true, or is general RAM used too?  What hardware is usually used for floating point arithmetic operations, data writing and reading?

2)  Are there extra SSE (or equivalent) bits after the end of absolutely all floating point registries, in a the 'Modern CPU'?  If not, how does the number registry/"extra registry" arrangement generally work?

3) How many 32 bit and 64 bit number floating point registries does the the 'Modern CPU' 64 bit system have available?

4) Are all of those 32 and 64 bit registries available to Java?  Can Java reuse one 64 bit registry as two 32 bit ones, or not?

The CPU-Z program, in the instructions entry, tells me that my the 'Modern CPU' happens to have the following instructions:

MMX, SSE, SSE2, SSE3, SSE4.1, SSE4.2, EM64T, VT-x,AVX.

I have been lead to believe that versions of SSE and beyond provide some extra mathematical binary data bits for assistance for range-limited, decimal point numbers, so that when on the right hand side of the binary number, when the 32 or 64 bit registry number runs out, as a result of base 10 arithmetic to binary,  that information straddling the end of the registry is given more binary space, so that the last decimal digit in the range never gets pronormal or denormal degrading values, due to discrepencies in concluding the binary pre representation for the decimal digits, due to the use formula:

(-1)s × m × 2(e - 127)

 5) How many bits are inside each extra SSE bit registry for the 'Modern CPU', presuming that extra bits past the end of 32 and 64 bit registers are of uniform length?  Is this number of bits constant or not, and if that varies, to what bit extent, and why?

0 Kudos
4 Replies
DeividA_Intel
Moderator
297 Views

Hello SM-1234, 



Thank you for the information provided 

 


I will proceed to check the issue internally and post back soon with more details. Bear in mind that, to provide some information we may need the CPU model since some specifications may be different from CPU to CPU.



Best regards, 

Deivid A.  

Intel Customer Support Technician 



SM-1234
Novice
285 Views

-Since my own CPU is too old for support purposes, I was thinking someone over there could just answer my questions by selecting some ubiquitous, up-to-the-moment, 64 bit Intel CPU.  I will monitor this thread for responses to my questions!

SM-1234
Novice
261 Views

Could all my questions above be applied to an Intel Core i9 Processor, i9-12900KS, at

https://ark.intel.com/content/www/us/en/ark/products/225916/intel-core-i912900ks-processor-30m-cache...

?

1)  I had thought that floating point binary digits are written and dealt with entirely inside the floating point unit of the 'Modern CPU'.  Is this true, or is general RAM used too?  What hardware is usually used for floating point arithmetic operations, data writing and reading?

2)  Are there extra SSE (or equivalent) bits after the end of absolutely all floating point registries, in the i9-12900KS'?  If not, how does the number registry/"extra registry" arrangement generally work?

3) How many 32 bit and 64 bit number floating point registries does the the i9-12900KS CPU have available?

4) Are all of those 32 and 64 bit registries available to Java?  Can Java reuse one 64 bit registry as two 32 bit ones, or not?

The CPU-Z program, in the instructions entry, tells me that my the 'Modern CPU' happens to have the following instructions:

MMX, SSE, SSE2, SSE3, SSE4.1, SSE4.2, EM64T, VT-x,AVX.

I have been lead to believe that versions of SSE and beyond provide some extra mathematical binary data bits for assistance for range-limited, decimal point numbers, so that when on the right hand side of the binary number, when the 32 or 64 bit registry number runs out, as a result of base 10 arithmetic to binary,  that information straddling the end of the registry is given more binary space, so that the last decimal digit in the range never gets pronormal or denormal degrading values, due to discrepencies in concluding the binary pre representation for the decimal digits, due to the use formula:

(-1)s × m × 2(e - 127)

 5) How many bits are inside each extra SSE bit registry for the i9-12900KS, presuming that extra bits past the end of 32 and 64 bit registers are of uniform length?  Is this number of bits constant or not, and if that varies, to what bit extent, and why?

DeividA_Intel
Moderator
235 Views

Hello SM-1234, 



In this case, I would like to inform you that do not provide support on how-to and/or development questions. However, you can find information related in the Intel® 64 and IA-32 Architectures Software Developer, Manual:



You can check specifically the Intel® Architecture Instruction Set Extensions Programming Reference section



Please keep in mind that this thread will no longer be monitored by Intel.  


Regards,  

Deivid A.  

Intel Customer Support Technician  


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