Typo in the sdm vol 3

[npopov]

Hello! I apologize if this message doesn't belong to the forum and should have been forwarded somewhere else.
While studying the current version of 'Intel® 64 and IA-32 architectures software developer's manual combined volumes 3A, 3B, 3C, and 3D: System programming guide' taken from this URL: https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html I encountered a possible typo that can mislead newcomers.
To be exact:
The chapter '4.10.3.1 Caches for Paging Structures' states that bits 56:40 of the linear address are used to search PML5E-cache. But it appears to be contradicting to other information about paging including that which is stated in the very same paragraph ["9-bit value"]. I suppose that bits 56:48 should have been here instead.
Thank you for your attention.

[JosueO_Intel]

Hello npopov,

Thank you for posting on the Intel communities. 

I will proceed to check the issue internally and post back soon with more details. 

Regards,

Josue O.  

Intel Customer Support Technician

[JosueO_Intel]

Hello npopov,

Hope you are doing great and staying safe, we are sorry for our late response. 

In this case, we can confirm this is a typo in the document. It has been noted and will be corrected in the next release of the document, however, we cannot promise an ETA. 

Thank you for reporting this to us. 

Hope this information is useful, if you need any additional information, please submit a new question as this thread will no longer be monitored. 

Regards,

Josue O.  

Intel Customer Support Technician