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sparsh18
Beginner
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Which cache eviction policy would you recommend for the L3 cache?

Screen Shot 2021-01-15 at 10.05.51 PM.png

 

Which cache eviction policy would you recommend for the L3 cache?

The cache block size is larger than the maximum data size operated on the processor. Explain whether this design would increase the hit rate or decrease the hit rate.

 

Please help me determine

  1. (i)  The generation number of this processor.

  2. (ii)  The number of logical processors.

  3. (iii)  The maximum core frequency when only half of the cores are active.

  4. (iv)  The maximum core frequency when only 1 core is active.

 

 

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3 Replies
Maria_R_Intel
Moderator
95 Views

Hello sparsh18,


Thank you for posting in the Intel* Community.


To better assist you, we would like to clarify some details:





 

Best regards, 

Maria R.  

Intel Customer Support Technician 


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Maria_R_Intel
Moderator
89 Views

Hello sparsh18,


Were you able to check the previous post?

 

Let me know if you need more assistance.

 

Best regards, 

Maria R.  

Intel Customer Support Technician 


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Maria_R_Intel
Moderator
21 Views

Hello sparsh18,


We have not heard back from you, so we will close this thread. If you need any additional information, please submit a new question as this thread will no longer be monitored.


Best regards, 

Maria R.  

Intel Customer Support Technician 


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