Which cache eviction policy would you recommend for the L3 cache?

[sparsh18]

Which cache eviction policy would you recommend for the L3 cache?

The cache block size is larger than the maximum data size operated on the processor. Explain whether this design would increase the hit rate or decrease the hit rate.

Please help me determine

1. (i)  The generation number of this processor.

2. (ii)  The number of logical processors.

3. (iii)  The maximum core frequency when only half of the cores are active.

4. (iv)  The maximum core frequency when only 1 core is active.

[Maria_R_Intel]

Hello sparsh18,

Thank you for posting in the Intel* Community.

To better assist you, we would like to clarify some details:

• Do you want to combine the amount of cache L3 with L1 to increase the capability?
• Can you please explain what do you mean by eviction policy?
• You can use this link to identify the Generation for your Intel® Core™ Processors https://www.intel.com/content/www/us/en/support/articles/000006059/processors.html

Best regards, 

Maria R.  

Intel Customer Support Technician 

[Maria_R_Intel]

Hello sparsh18,

Were you able to check the previous post?

Let me know if you need more assistance.

Best regards, 

Maria R.  

Intel Customer Support Technician 

[Maria_R_Intel]

Hello sparsh18,

We have not heard back from you, so we will close this thread. If you need any additional information, please submit a new question as this thread will no longer be monitored.

Best regards, 

Maria R.  

Intel Customer Support Technician