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I have an Intel Xeon E5-2667 v3 and am working with the Linux ioatdma driver (device IDs 0x2f20..0x2f27).
The only Intel documentation I've found are the Xeon E5 v3 datasheets (vols 1 & 2). Vol 2 has the register layout, but no operational description, descriptor formats, etc.
I'm trying to use the DMA engine to transfer from PCIe memory (non-prefetchable) to system memory, but the PCIe address gets reported as an invalid source address (chanerr::dma_trans_saddr_err). The data that gets written appears to be stale data in the ioatdma internal (64 byte?) DMA buffers.
If I swap the addresses, i.e., write to PCIe, everything works fine.
At this point I have to assume ioatdma is sending a read request that gets a bad completion of some kind (bad status or poisoned?). Not sure how to chase this down further within chip. Or other variation I can try -- seems like the primary ioatdma use case is memcpy between 2 system memory locations.
(I'm trying to work this from the PCIe endpoint as well.)
- Tags:
- PCIe
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Hi 0xDEAN, please check the following links:
- http://www.intel.com/support/network/adapter/pro100/sb/CS-031576.htm Intel® Server Adapters — Where to Get the IOATDMA Driver for Linux*
- http://www.intel.com/content/dam/doc/white-paper/quickdata-technology-software-guide-for-linux-paper.pdf http://www.intel.com/content/dam/doc/white-paper/quickdata-technology-software-guide-for-linux-paper.pdf
- http://web.mit.edu/cron/documentation/dell-server-admin/en/IntelNIC/ioat.htm Intel I/O Acceleration Technology: Intel Network Adapters User Guide
- http://lxr.free-electrons.com/source/drivers/dma/ioat/dma.c Linux/drivers/dma/ioat/dma.c - Linux Cross Reference - Free Electrons
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I've found out through other channels that ioatdma v3.2 doesn't support reading from PCIe/MMIO.
Apparently v3.3 does. I haven't been able to confirm this in any publicly available documentation.
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You may get a better response by posting your question here: https://software.intel.com/en-us/forum https://software.intel.com/en-us/forum
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