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what is the cache line eviction policy for non-inclusive shared L3 ?

Alam__Shariful
New Contributor I
496 Views

In Intel Skylake X processors, I found that each core has one private L1 cache, private L2 cache, and shared non-inclusive L3 cache. However, I could not find any information regarding caching policy of L2. Is it inclusive of L1?

Now, regarding the non-inclusive shared L3, what happens if a cache line is removed from L3? Particularly, if a cache line is removed from shared non-inclusive L3, will L1 still hold that data? If yes, is it guaranteed that L1 will always keep the data unless L1 is full? 

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5 Replies
Alberto_R_Intel
Moderator
471 Views

Alam__Shariful, Thank you for posting in the Intel® Communities Support.


In order for us to provide the most accurate assistance on this matter, we just wanted to confirm a few details about your system:

What is the model of the Intel® processor?

Is there any particular reason why you are requesting that information?

Are you a developer?

Are you working on a project?

Are you building, designing, or modifying hardware/software?

Are you working with a specific Intel® hardware/software platform?


Any questions, please let me know.


Regards,

Albert R.


Intel Customer Support Technician


Alam__Shariful
New Contributor I
466 Views

Hi Albert,

Thank you for your reply. 

 

What is the model of the Intel® processor? - Intel Core i7-6700

Is there any particular reason why you are requesting that information? - I was trying to see if I can get any benefit from the requested information.

Are you a developer? No

Are you working on a project? Yes

Are you building, designing, or modifying hardware/software? Yes

Are you working with a specific Intel® hardware/software platform? Yes

 

Regards,

Shariful Alam

Alberto_R_Intel
Moderator
452 Views

Hi Alam__Shariful, You are very welcome, thank you very much for providing that information.


We will do further research on this matter, as soon as I get any updates I will post all the details on this thread.


Regards,

Albert R.


Intel Customer Support Technician


Alberto_R_Intel
Moderator
438 Views

Hello Alam__Shariful, Just an update on this matter. 


We are still working on this case, as soon as I get the details requested I will post them on this thread.


Regards,

Albert R.


Intel Customer Support Technician


Alberto_R_Intel
Moderator
411 Views

Hello Alam__Shariful, I just received another update on this case.


In reference to your questions, you can always verify the details in the official developer manual, please visit the link below in order to see them (Chapter 11 - Memory Cache-Control):

https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software... 


If by any chance you have further questions on this topic, please visit, sign in, and submit your inquiries in our Intel® Developer Zone website, where you will be able to receive further peer to peer assistance on this matter:

https://community.intel.com/t5/Software/ct-p/software-products


Regards,

Albert R.


Intel Customer Support Technician



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