I would recommend to look to the similar thread with the topic of: Will the 5CEFA4U19 chip work without some power pins connected as suggested by the Quartus migration feature.
I would recommend to look to Intel MAX 10 FPGA Device Family Pin Connection Guidelines (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf)
There is the following fragment as an explanation of NC pin, section Reference Pins, p.12:
Pin Name = NC, Pin Type = No Connect, Pin Description = Do not drive signals into these pins. Connection Guidelines = When designing for device migration, these pins may be connected to power, GND, or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern, leave these pins floating.
According to the previous response in the mentioned thread from the user sreekumar.regu.girijakumari from Intel and my own experiences with MAX 10 and Arria 10 families I assume it is OK.
I believe this kdb will clear your doubt about connecting NC to IO: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...
As for K3, GND to NC, in this case your 10M40 will be lacking 1 GND pin. We do not recommend it as this is not tested.