Community
cancel
Showing results for 
Search instead for 
Did you mean: 
hsong22
Beginner
228 Views

10663 parameter or port?

屏幕截图(281).png

0 Kudos
3 Replies
Vicky1
Employee
46 Views

Hi,

here, you have used the 'DIVPA' parameter for instantiation of module 'clkdiv' & it might not be legal.

please refer the 'Verilog LRM' for '3.4 Parameters ', here it is mentioned that It is not legal to use hierarchical name referencing (from within the analog block) to access external analog variables or parameters.

https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf

Regards,

Vicky

Vicky1
Employee
46 Views

Hi,

May I know any update or Should I consider that case to be closed?

Regards,

Vicky

 

hsong22
Beginner
46 Views

Oh!sory!yeah, I have found the problem that in some other part the parameter k is defined by wrong spell word, I spell input as inout..you can close it now, thank you! 发送自 Windows 10 版邮件<https://go.microsoft.com/fwlink/?LinkId=550986>应用
Reply