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10663 parameter or port?

hsong22
Beginner
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屏幕截图(281).png

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3 Replies
Vicky1
Employee
122 Views

Hi,

here, you have used the 'DIVPA' parameter for instantiation of module 'clkdiv' & it might not be legal.

please refer the 'Verilog LRM' for '3.4 Parameters ', here it is mentioned that It is not legal to use hierarchical name referencing (from within the analog block) to access external analog variables or parameters.

https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf

Regards,

Vicky

Vicky1
Employee
122 Views

Hi,

May I know any update or Should I consider that case to be closed?

Regards,

Vicky

 

hsong22
Beginner
122 Views
Oh!sory!yeah, I have found the problem that in some other part the parameter k is defined by wrong spell word, I spell input as inout..you can close it now, thank you! 发送自 Windows 10 版邮件<https://go.microsoft.com/fwlink/?LinkId=550986>应用
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