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Altera_Forum
Honored Contributor I
2,321 Views

10779 VHDL ERROR : expression is not constant

Hello guys, 

I am writing VHDL code in Quartus Prime 15.1 Lite Edition. I have problem when I was doing Analysis and Synthesis. 

The error is expression is not constant. 

I can use that data(a downto b ) assign the signal in the code. But a and b are variable. 

 

I search the problem in altera site so I found. It said " Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error message if you use a variable as an index for signal" 

 

But my program is update and I can use quartus 15.1, so I think The error doesn't occur.  

 

Why does the error occur ? 

How to solve the problem ? 

What do u think of the problem related to library ??? 

0 Kudos
10 Replies
Altera_Forum
Honored Contributor I
106 Views

Can you post the code? Without that there is little we can say

Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

Can you post the code? Without that there is little we can say 

--- Quote End ---  

 

 

Firstly, thank u for replying my problem 

 

I added my file as attachment.You can look in the attachments. 

 

In the altera_code.PNG ; msg_id_count is variable and integer signal. I can use variable because ı want to do generic and like shift register. 

 

Actually, I dont understand why did the error occur in the 15.1 versiyon. 

 

I find my problem's solution in the altera site, you can look in the altera_problems_solution.jpg.  

 

my versiyon is updater than 13.1 altera versiyon, but THE ERROR occur when I was doing SYNTHESIS.
Altera_Forum
Honored Contributor I
106 Views

you didnt attach the code, just a tiny snippet. Please post the whole code so we can see whats going on. Not just the line with the issue.

Altera_Forum
Honored Contributor I
106 Views

But it could be that this is still a problem, and you'll have to work around it. Usually you can do this with a case statement instead of a slice

Altera_Forum
Honored Contributor I
106 Views

I added my code file, When u are going to look my code, I express the error command near to my code. 

 

I hope u will find solution . 

 

Thank u ...
Altera_Forum
Honored Contributor I
106 Views

There is nothing wrong with the code. I suspect the problem is just with quartus. And although the website you found only mentions 13.1, The problem may have persisted. I remember this issue from a long time ago (8/9 years ago), maybe it never got fixed. Have you tried in a newer version of Quartus? 

 

Other than that, the work around is to use ifs or a case statement: 

 

case msg_id_count is when 3 => uart_tx_data_s <= tx_id_s(23 downto 16); when 2 => uart_tx_data_s <= tx_id_s(15 downto 8); when 1 => uart_tx_data_s <= tx_id_s( 7 downto 0); when others => report "Illegal value for msg_id_count" severity FAILURE; -- simulation case to catch illegal value of msg_id_count end case;
Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

There is nothing wrong with the code. I suspect the problem is just with quartus. And although the website you found only mentions 13.1, The problem may have persisted. I remember this issue from a long time ago (8/9 years ago), maybe it never got fixed. Have you tried in a newer version of Quartus? 

 

Other than that, the work around is to use ifs or a case statement: 

 

case msg_id_count is when 3 => uart_tx_data_s <= tx_id_s(23 downto 16); when 2 => uart_tx_data_s <= tx_id_s(15 downto 8); when 1 => uart_tx_data_s <= tx_id_s( 7 downto 0); when others => report "Illegal value for msg_id_count" severity FAILURE; -- simulation case to catch illegal value of msg_id_count end case;  

--- Quote End ---  

 

 

Thank u , I can try your expression , I hope The problem will be solved by Altera. Because Generic action is very important with our project. 

of course ,I know if or case statement. :) But &#305;f I use case statement , I have to change my code Different project. We want to use like IP core. 

We can try analys&#305;s Vivado program , The error is not occur. But my favourite program is Altera. I hope the promlem will solve in the future. 

Thanks , repeat =)
Altera_Forum
Honored Contributor I
106 Views

Have you tried quartus 17?

Altera_Forum
Honored Contributor I
106 Views

 

--- Quote Start ---  

There is nothing wrong with the code. 

--- Quote End ---  

 

 

Tend to disagree here. 

 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE ieee.numeric_std.ALL;  

 

the code is mixing old and new, standard and non-standard (i.e. incompatible) libraries. I didn't check in detail, but it might well be the case that this is causing hidden conflicts. 

 

@ocy: I would propose you to limit yourself to the official ieee libraries: 

 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL;  

 

Throwing in everything at random is asking for trouble, IMHO. 

 

P.S.: after this change (and a few related changes necessary because of this), your code synthesised fine for me with 13.1. I would assume the same for later Quartus versions.
Altera_Forum
Honored Contributor I
106 Views

@mfro 

 

Mixing these libraries is NOT a problem. The ONLY problem is if the user tried to use unsigned/signed type - there is a library clash between numeric_std and std_logic_arith as they both declare these types, so they are all hidden from the user, forcing the user to be explicit about which one to use. They are otherwise fully compatible, and all basically produce the same logic when used. 

 

While it is best practice to only use numeric_std, its also good to know how the libraries and packages work.  

If it is the libraries causing the problem, it is a defect with Quartus, not with the VHDL code.