10CL016YF484C8G Power On Sequence

[Jq6313]

Does anyone know if there is a supply rail power on sequence for this FPGA? As in does the supply rails have to be powered in a certain order?

[FvM]

Hi,
the information is a bit hidden in device handbook paragraph 9.4 Power-on reset circuitry:

The POR circuit of the Intel Cyclone 10 LP device monitors the VCCINT, VCCA, and VCCIO (of banks 1, 5, 6, and that contain configuration pins during power-on. You can power up or power down the VCCINT, VCCA, and VCCIO pins in any sequence. The VCCINT, VCCA, and VCCIO must have a monotonic rise to their steady state levels. All VCCA pins must be powered to 2.5V (even when phase-locked loops [PLLs] are not used), and must be powered up and powered down at the same time.

[Farabi]

Hello,

I am sorry for late reply. I am taking over this case as previous owner is no longer with our team.

You can power up or power down the VCCINT, VCCA, and VCCIO pins in any sequence. The VCCINT, VCCA, and VCCIO must have a monotonic rise to their steady state levels. All VCCA pins must be powered to 2.5V (even when phase-locked loops [PLLs] are not used), and must be powered up and powered down at the same time.

link : https://www.intel.com/content/www/us/en/docs/programmable/683777/current/power-on-reset-circuitry.html

regards,

Farabi

[Farabi]

Hello,

I have provided you the answer to your question and this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,

Farabi