10CX105YF672FPGA: question about the INIT_DONE pin voltage

[GhamdiASA]

Hello,

We are designing a circuit that uses 10CX105YF672. We want to enable the INIT-DONE function, and in the pin connection guidelines document, it says to connect the pin to VCCPGM (1.8V in our design) through a 10K resistor. However, we are using the 2A bank (as seen in the picture below) for the 1.35V DDR3L interface. In this case, can we connect the INIT-DONE pin to 1.8V without an issue?

Thanks

[Fakhrul]

Hi GhamdiASA,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding.

[Fakhrul]

Hi,

For INIT_DONE pin, this is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE.

When using as optionally open-drain output dedicated INIT_DONE pin, a transition from low to high at the pin indicates when the device has entered user mode. The INIT_DONE pin cannot be used as a user I/O pin after configuration. Connect this pin to an external 10-kΩ pull-up resistor to VCCPGM. 

When using in an AS or PS multi-device configuration mode ensure INIT_DONE is enabled in the Quartus Prime design. When not using as the dedicated INIT_DONE pin, and when this pin is not used as an I/O pin, then connect this pin as defined in the Quartus Prime software.

Thanks,

Fakhrul