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Valued Contributor III
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10M02DCV36I7G - cheap, reliable clocking

I am new to MAX10s and pretty new to FPGAs in general, and will be using 10M02DCV36I7G as a peak detector. The inputs come from two single-ended comparator outputs. 

 

I plan to use a number of phase-shifted clocks to minimize the timing uncertainty for when the peak was detected. For example four separate 400 MHz clocks each shifted a quarter period in relation to each other would give an uncertainty of 625 ps. 

 

The design needs to be low cost, low power and reliable, and I'm wondering if there is a downside to using a 5 MHz external crystal/oscillator with the 10M02 V36's internal PLL to generate four or five 400 MHz clocks. 

 

Anyone have some insights on this?
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Valued Contributor III
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A 25MHz or 50MHz would probably be a better choice than 5MHz; as these frequencies are very common and the devices are readily available. 

Multiplication factor would be 10X smaller at 50MHz vs 5MHz, s depending on the characteristics of your 5MHz device you might get better jitter performance at 50MHz. 

5MHz is the absolute minimum input frequency to the PLL on a MAX10, so you would be right at the limit of the device capability.
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Valued Contributor III
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Are you sure the MAX 10 fabric is fast enough to do what you need at 400MHz? The clock tree is rated for 416MHz in your speed grade, and the PLLs can handle 400MHz, but that doesn't mean you can do any real work at that frequency. I normally gauge the fabric speed by how fast the internal hard blocks can run (e.g., RAMs and multipliers). In an I7 MAX 10 18x18 multipliers are rated at 240MHz and M9K blocks are rated at 300MHz (both assume dual supply mode). Depending on what you're doing 400MHz sounds extremely aggressive. And multiple phases at 400MHz sounds off-the-charts aggressive. 

 

As for using an internal PLL to generate the 400MHz clocks, my main concern would be jitter. The PLL output jitter spec is 300ps (max). That's a ton of jitter for a 400MHz clock. In fact 300ps represents about 1/8th of the clock period, or about 45 degrees. It also represents about half of your uncertainty spec. 

 

To solve the jitter problem you could use an external quad clock generator like the Silicon Labs Si5338 that is used on a lot of Altera dev kits. I've used that device in several designs and they're great - and very low jitter. It may not fit within your "cheap" requirement but you may not have a choice given your design specs. 

 

Tough design. Good luck.
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Valued Contributor III
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The point is to do peak detection, so there is not a lot involved at the high frequency. I could run a lower main frequency, and synchronize the peak detectors to that. Four phases of 400 MHz is not a hard requirement, but I am looking to minimize the timing uncertainty when detecting the peaks, and trying to uncover the pros and cons of various solutions. 

 

Thanks for pointing out the HW limitations and jitter concerns, which are of course important. The Si5338 is waaaay too expensive unfortunately. I have to keep this dirt cheap. 

 

Given the high jitter and other concerns, it might make sense to run four phases of 200 MHz. 

 

Are there considerably power savings to having a low scaling factor between oscillator input and PLL output? Or other advantages?
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Valued Contributor III
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--- Quote Start ---  

The point is to do peak detection, so there is not a lot involved at the high frequency. I could run a lower main frequency, and synchronize the peak detectors to that. Four phases of 400 MHz is not a hard requirement, but I am looking to minimize the timing uncertainty when detecting the peaks, and trying to uncover the pros and cons of various solutions. 

 

Thanks for pointing out the HW limitations and jitter concerns, which are of course important. The Si5338 is waaaay too expensive unfortunately. I have to keep this dirt cheap. 

 

Given the high jitter and other concerns, it might make sense to run four phases of 200 MHz. 

 

Are there considerably power savings to having a low scaling factor between oscillator input and PLL output? Or other advantages? 

--- Quote End ---  

 

 

 

I'm a bit unclear on the peak detection process, could you elaborate? I don't think there are significant power savings with PLL scaling factors but others may have more knowledge here.
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Valued Contributor III
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--- Quote Start ---  

Are there considerably power savings to having a low scaling factor between oscillator input and PLL output? Or other advantages? 

--- Quote End ---  

 

 

Dynamic power dissipation in CMOS is directly related to switching frequency, so slowing the clocks down will definitely reduce power. But that would be more in the clock trees and logic fabric. The power savings in the PLL itself would probably not be significant.
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Valued Contributor III
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I have external comparators detecting the higher voltage peaks of a 5-30 MHz sinus of varying amplitude, and intend to use a couple of Flancters* to measure the delay from T=0 to each of the peaks. I can accept some delay in the signal chain as long as it is deterministic (and as long as the Flancter can reset between same-polarity peaks), but I must keep the unknown delays, ex. from overdrive dispersion or jitter, to a minimum (within reason), hence the idea to use multiple phase-shifted same-frequency clocks. 

 

Given that higher frequency oscillators cost more and use more power, it seems like the best choice in this case is to use the PLL, and deal with the jitter. 

 

https://www.doulos.com/knowhow/fpga/fastcounter/ 

http://www.floobydust.com/flancter/flancter_app_note.pdf
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Valued Contributor III
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If you have the luxury of making repetitive measurements on the same signal, then you could dynamically shift the phase of the PLL (rather than using multiple phase-shifted outputs) and average multiple readings to reduce the effects of random jitter.

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Valued Contributor III
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I wonder, couldn't I use LVDS/LVPECL inputs on the MAX 10 as comparators with some debounce hw acting as a sort of hysteresis? That would save me an external comparator _and_ some propagation delay.

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Valued Contributor III
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Some development kits are using FPGA LVDS input as comparator together with an external RC circuit to make a poor-man's sigma-delta ADC. In so far it's surely possible. Biggest problem may the lack of complete analog behavior specifications.

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Valued Contributor III
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Interesting. 

 

Do you think in such a comparator setup, that I could use the LVDS/LVPECL input as a clock input, with FFs clocking off both the rising and falling edges? 

 

That would allow me to capture the comparator events with practically no delay. 

 

https://s4.postimg.org/hhc5yudzh/fpga_clock_input.png (https://postimg.org/image/40f7fz3nt/)free upload (https://postimage.org/)
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Valued Contributor III
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Just tried it on the 10M08 eval board, and it works great :)

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