10M04SCU324I7G - I/O timing

[chris_gonzalez9]

I would like to know if those values are the minimum, nominal or maximum. Thanks!

[Kenny_Tan]

If you refer to device datasheet, this device itself will not show it is min/norminal/max/ value.

https://www.intel.com/content/www/us/en/docs/programmable/683794/current/fpga-device-datasheet.html

You can refer to https://www.intel.com/content/www/us/en/docs/programmable/683103/21-3/step-4-view-i-o-timing-in-datasheet-report.html

Any reason that you need this value? thanks

[chris_gonzalez9]

Hi Kenny, 

I'm working on some timing analysis using timing designer and I wanted to know whats the minimum, nom or maximum to set those time constrains in timing designer.

[Kenny_Tan]

I will need more time to look into this, I will get back to you.

[Kenny_Tan]

Generally, you may use this method to get your IO timing https://www.intel.com/content/www/us/en/docs/programmable/683103/21-3/generating-initial-i-o-timing-data-for-fpgas.html

Base on my understanding, you are trying to get the min and max from here https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562?

If yes, below is some answer that will help you:

when you're setting output constraints with set_output_delay, you need to know the relative timing between the FPGA and the external device, especially the clock delay differences. The min and max output delays are derived from system-level timing analysis, which includes both board delays and device specs.

Example of the formulas:

tD_CLK(max) = tD_CLK_DEV(max) - tD_CLK_FPGA(min)

tD_CLK(min) = tD_CLK_DEV(min) - tD_CLK_FPGA(max)

These refer to clock arrival times at the external device (DEV) and the FPGA.

So where do you get these values?

1. From Board-Level Analysis:

tD_CLK_DEV(max/min): Measure or estimate how long the clock takes to travel from the clock source (like an oscillator or another device) to the destination device. Include PCB trace delay, routing skew, and any buffer or level shifter delay.

tD_CLK_FPGA(max/min): Same idea, but to the FPGA clock input pin.

Board delay variation (max/min) comes from:

PCB trace length mismatches (measured or simulated using tools like HyperLynx, Allegro, etc.)

Manufacturing variations

Signal integrity simulation or timing budgets from the board designer

2. From Datasheets / Timing Specs:

For device delays, especially internal timing paths or setup/hold requirements, check the timing characteristics in the receiving device's datasheet.

For FPGA side, look at IO timing (from Quartus TimeQuest timing report — e.g., output min/max delays, clock-to-out, etc.).

TL;DR: How to get tD_CLK(min/max)

Value Source

tD_CLK_DEV(max/min) PCB timing simulation or measured board delay

tD_CLK_FPGA(max/min) PCB + FPGA input clock path (pin to PLL, etc.)

[Kenny_Tan]

Not sure if you have further question?

[Kenny_Tan]

Not sure if you have further question?

[Kenny_Tan]

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