10M08DAF256 - LVDS rx-only, can IO bank be at 3.3V?

[akohlsmith]

Subject says it all; I have a 10M08D and I have accidentally connected bank 5 and 6 to my 3.3V supply and not a 2.5V supply as is specified for LVDS I/O. I am not sure how this managed to get past the review but it's a pretty glaring bug. :-(

I may have a hail mary in that the LVDS I/O on these two banks is *only* receiving; I am not driving any LVDS IO with the FPGA.

Is it possible that I may be able to use these boards with this rather serious error? What are my potential implications (SI, speed, etc.) if this does work?

Thank you.

[SreekumarR_G_Intel]

Thank you giving opportunity to look at issue, Can I assume few things from your input , i) You are not plan to use LVDS in the board using FPGA. Correct ? ii) The VCCIO of bank 5 and 6 connected to the 3.3V. Also Can I assume VREFBx pin is not used for reference voltage ? Correct If my above assumption yes , I don’t think so there is issue to connect the 3.3V bank 5 and bank 6 . In the datasheet can you refer page 7 for the max apply VCCIO ? Note : VCCA must connected to the 2.5V. May I know why you think bank 5 and 6 need to use only for LVDS ? Thank you, Regards, Sree

[akohlsmith]

Hello, thank you for your assistance. 

This is is a prototype design which has already been laid out. The final design will of course have the correct IO voltage. 

I have a number of LVDS inputs on bank 5 and 6. They are externally terminated with 100 ohm resistors. The FPGA is not transmitting any LVDS, only receiving. I have mistakenly connected bank 5 and 6 VCCIO to 3.3V instead of 2.5V as specified in the data sheet. You are correct that VREFB is not used as reference; those pins are used as regular, low speed single ended I/O. 

Yes, VCCA is connected to 2.5V. VCCA_ADC and ADC_VREF are also connected to 2.5V. VCCD_PLL1/2, VCC_INT and VCC are all connected to 1.2V with filters as specified in the pin connection guidelines on page 26.

My question is if the 10M08D will be able to correctly receive 125MHz LVDS (250Mbps) on bank 5 and 6 with VCCIO at 3.3V instead of 2.5V. I am not transmitting, only receiving. I want to know if I can use these boards or if I must scrap them and re-spin the prototypes due to this mistake.

Thank you,

-A.

[SreekumarR_G_Intel]

Hello , Apologies for delay in response ,

The problem here is Receiver LVDS and it internal block is now powered by 3.3V instead of 2.5V which is not designed for.

I am sorry It is not recommended to use the 3.3V on the LVDS. We cant guarantee the device work as mentioned in intel document.

Thank you ,

Regards,

Sree

[akohlsmith]

Thank you again for your response.

I understand it is not recommended and that performance is not guaranteed; the datasheet makes clear that the proper voltage for banks with LVDS is 2.5V. My question is whether the LVDS receivers will work (perhaps with degraded performance) with VCCIO at 3.3V. If the LVDS receivers will work with an out-of-spec VCCIO, what can I expect in terms of performance degradation (change of switching threshold or margin, reduced max speed, etc.) on the LVDS inputs? Surely Intel has some data on this kind of application and can give me an idea of what I might expect.

I'm trying to see whether I scrap these boards and order new ones or if I can work with the reduced performance for these prototypes, and only make the corrections on the new boards.

These are answers I cannot obtain without Intel's help.

[SreekumarR_G_Intel]

Hello there , i am sorry we wont able to help on this scenairo. Worst case is you can power up the board and see. Sorry my input not much helpful to you :( Thank you , Regards, Sree