10M08SCU169C8G power consumption

[tony567]

Dear Intel:

     we implement 10M08SCU169C8G in our board, we are drawing schematic now, we don't begin coding yet, but we need know the 10M08SCU169C8G power consumption for board layout, power map, power budget assess, it's very very very diffcult to use the estimator to calculate the current, could you please tell me directly the power consumption of 10M08SCU169C8G? I can't get support from IBL, they told me I can get support here!!! please help!!!

[JonWay_C_Intel]

Hi,

If you have already started drawing schematic, I would assume that you have already done some planning. One of the planning is the power budgeting. To do so, you need to estimate how much resources that you are going to use. I would suggest that you to download the EPE link here.

Note that there is no fixed number for power consumption. How much power it consumes depends on how much resources you use.

Another thing that I would suggest you to refer is the Pin Connection Guideline. link here.
This would give you an idea how your pins are supposed to be connected.

[tony567]

Dear JonWay,

     actually, We've got the EPE spreadsheet from different channels, but no one can tell clearly how to fill the excel sheet!!! we are hardware engineer, not CPLD coding engineer, most glossary used in that sheet mean nothing to us, it's very very very very very diffficult to fill in that so called EPE file, it's so bad!!! we just need the power consumption for power map drawing, routing plan, tha's all at current stage!!! why do intel consider every hardware designer know VHDL, and familiar with the glossary used in that sheet?! this not make sense!!! do you really survey every designer implement your FPGA/CPLD have the ability to code and understand so many glossarys used in that **bleep** sheet???!!!

[JonWay_C_Intel]

Hi there,

I understand your frustration if you are new to FPGA design.
I would suggest that you take one-step at a time.

Firstly, to get a general idea about EPE, watch the following youtube video: https://www.youtube.com/watch?v=5IMLMiBxIKE
Or for more detailed training: https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/power-support.html

Going back to your problem statement: Can we provide a power consumption number?
Frankly- No. Why? Because each FPGA design is different, and thus the power consumption is different.
However, I can guide you towards that number based on your design.

It takes some cooperation between the Hardware Engineer such as yourself, the RTL engineer and Thermal engineer to get started.
There must be some team planning that has already been done before you should get started, thus I believe there are already some info that you can use to plug into the EPE.

1) RTL engineers should have done some floorplanning and identifying what IPs are needed. Also, I expect that the RTL engineers would already have some RTL in-testing. At this stage, you should already have a design skeleton....and this is a good starting point.
RTL engineer can provide a EPE import file. Follow the steps here: https://www.youtube.com/watch?v=NntUdw7EOc0

2) Thermal Engineer should have some planning on what kind of cooling solutions. How much airflow, what kind of heatsink, etc. Why you need this info? Because the cooler the fpga, the lower the static power, thus lower power consumption. Select the cooling solution in the EPE that best reflect your design.

3) Combine the info from (1) and (2), populate the EPE. From the EPE, you will have an idea how much current each rail consumes. Then, as hardware engineer, you can proceed to design your power tree.

I hope this helps.

[tony567]

Dear JonWay,

     1. you are talking about some ideal situation, and I am stopped by practical issue! we don't have so much resource to do this! I can not get any support except IC vendor, you are wasting my time!

     2. our project are in RFQ concept stage, I can get no one CPLD engineer help, I only have myself to do this, we need complete schematic, and provide board file to customer, 

    3. you just need tell me the MAX current that IC will sink, 

    4. you need know that CPLD engineer have extra much time for coding after the board gerbered out, PCB fabrication will need about half a mouth, usually this period is good for coding, CPLD engineer can tell you nothing at concept stage!!!

    5. INTEL FPGA BAD SUPPORT!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**dog**bleep**