Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21600 Обсуждение

1GB RAM demands all available Addresses(SOPC Builder)

Altera_Forum
Почетный участник II
1 755Просмотр.

Hey,  

I use a Stratix III board with 1 GB of DDR2 Dimm(Micron MT9HTF12872AY-800E1 1GB(1152MB), DDR2, 800MHZ CL6). I use the DDR2 SDRAM HIGH Performance Controller. The SOPC builder tells me that it needs 2 gigs of addresspace(0x0 - 0x7FFFFFFF) So thats exactly 2 gigs of RAM and I only got 31 address bits(SOPC Builder tells me). So this demands all of my address memory. But I also use other MM-Slaves.  

So what can I do? Why do I only have 31 address lines? One of my Avalon MM Slave devices also MUST be located at address 0x00. So the DDR2 Controller must be located at address 0x80000000 - 0xFFFFFFFF. Please help me. What can I do?
0 баллов
10 Ответы
Altera_Forum
Почетный участник II
922Просмотр.

Problem solved. I just activated "Enable error detection and correction logic" so this seperates the ecc stuff to an owen port and so i just need a bit more then 1 gig of ram instead of 2 gigs :)

Altera_Forum
Почетный участник II
922Просмотр.

Adressbit 31 is used for cache bypass. 

so you only have bit 0 to 30 meaning 31 bit at all.
Altera_Forum
Почетный участник II
922Просмотр.

Where can I find "Enable error detection and correction logic" option?

Altera_Forum
Почетный участник II
922Просмотр.

SOPC Builder: click on options for the ddr2 SDRAM High Performance Controller and then click on the tab Controller Settings. 

 

 

 

 

OK: It works that way: 

Add the DDR2 SDRAM High Performance Controller. Do your settings at the Memory tab as well as at the PHY Settings Tab. Then click on the Controller Settings Tab and select "Enable error detection and correction logic". 

The click on ok(So u use only 30 Bits for 1 Gig of Ram). 

Then add a Avalon_MM Clock Crossing Bridge 2 times. Connect 1 to the S1-Port of the DDR2 Controller and the other to the ecc_slave port. The Addresses of the DDR2 Ram should start both at address 0x0(Otherwise you need more memory at the Clock Crossing Bridgets WITHOUT ANY advanteges!  

I hope I wrote it clearly. At least my SOPC builder generates vhdl-code and i only need 0x4000400 memory addresses instead of 0x8000000.
Altera_Forum
Почетный участник II
922Просмотр.

oops !! it seems like I cannot use the DDR2 SDRAM High Performance Controller, since it is not supported in Cyclone II. 

Anyway i solved the main problem by separating the addresses far away so it works now. 

I am wondering if there is a way to use the DDR2 SDRAM High Performance Controller in Cyclone II!
Altera_Forum
Почетный участник II
922Просмотр.

Well I am using the Stratix III Board. Do you have a DDR2 Dimm -Slot in your Cyclone II Board(U use the normal x86 DDR RAM).

Altera_Forum
Почетный участник II
922Просмотр.

I have a slot. But what is the relation between the SDRAM type and using the "DDR2/DDR SDRAM High Performance Controller" since both are not supported by the Cyclone II?

Altera_Forum
Почетный участник II
922Просмотр.

Well if u got a slot, then u got some support for that. I took a quick look at the manual. DDR2 is supported. btw. There are 2 DDR2 Controllers available at the SOPC builder. I can only use the high speed ddr2 controller. Not the other one. Maybe its vice versa for you or u have to use the mega wizard thing.

Altera_Forum
Почетный участник II
922Просмотр.

yes it's vice versa. 

If you meant to use the MegaCore, then this is what I am using now but actually I need to speed up the DDR2 performance because I am using it to display frames with the VGA decoder and I cannot reach the refresh rate of it which is 60 fps (i.e. 25 MHz VGA clock.)
Altera_Forum
Почетный участник II
922Просмотр.

Well, rtfm. Look at the adjust possibilities.

Ответить